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MT5C2568 Datasheet(PDF) 5 Page - Austin Semiconductor

Part No. MT5C2568
Description  32K x 8 SRAM SRAM MEMORY ARRAY
Download  16 Pages
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Maker  AUSTIN [Austin Semiconductor]
Homepage  http://www.austinsemiconductor.com
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MT5C2568 Datasheet(HTML) 5 Page - Austin Semiconductor

 
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SRAM
SRAM
SRAM
SRAM
SRAM
MT5C2568
AS5C2568
MT5C2568 / AS5C2568
Rev. 4.5 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
Austin Semiconductor, Inc.
NOTES
1.
All voltages referenced to V
SS (GND).
2.
-3V for pulse width < 20ns
3.
I
CC is dependent on output loading and cycle rates.
The
specified value applies with the outputs unloaded, and
f =
1
Hz.
tRC (MIN)
4.
This parameter is guaranteed but not tested.
5.
Test conditions as specified with the output loading as
shown in Fig. 1 unless otherwise noted.
6.
t HZCE, tHZOE and tHZWE are specified with CL = 5pF
as in Fig. 2. Transition is measured ±500mV typical from
steady state voltage, allowing for actual tester RC time
constant.
7.
At any given temperature and voltage condition, tHZCE
is less than tLZCE, and tHZWE is less than tLZWE.
8.
WE\ is HIGH for READ cycle.
9.
Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. tRC = Read Cycle Time.
12. Chip enable (CE\) and write enable (WE\) can initiate and
terminate a WRITE cycle.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
LOW Vcc DATA RETENTION WAVEFORM
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DON’T CARE
UNDEFINED
AC TEST CONDITIONS
Input pulse levels....................................................Vss to 3V
Input rise and fall times.....................................................5ns
Input timing reference level.............................................1.5V
Output reference level......................................................1.5V
Output load.................................................See figures 1 & 2
DESCRIPTION
CONDITIONS
SYM
MIN
MAX
UNITS
NOTES
VCC for Retention Data
VDR
2V
Data Retention Current
CE\ > (VCC-0.2V)
VIN > (VCC-0.2V)
or < 0.2V
ICCDR
1mA
Chip Deselect to Data
Retention Time
tCDR
0--
ns
4
Operation Recovery Time
tR
tRC
ns
4, 11
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12
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DATA RETENTION MODE
V
DR > 2V
4.5V
4.5V
V
DR
tCDR
tR
V
IH
V
IL
V
CC
CE\
Fig. 2
OUTPUT LOAD
EQUIVALENT
Fig. 1
OUTPUT LOAD
EQUIVALENT
+5V
Q
255
30 pF
480
5 pF
+5V
Q
255
480


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