AS4DDR232M72PBG datasheet(5/28 Pages) AUSTIN

Part #	AS4DDR232M72PBG

Description	32Mx72 DDR2 SDRAM iNTEGRATED Plastic Encapsulated Microcircuit

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Manufacturer	AUSTIN [Austin Semiconductor]

Direct Link	http://www.austinsemiconductor.com

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iiiiiPEM

PEM

2.4 G

2.4 Gbbbbb SDRAM-DDR2

SDRAM-DDR2

AS4DDR232M72PBG

Rev. 2.0 5/07

Austin Semiconductor, Inc. ● Austin, Texas ● 512.339.1188 ● www.austinsemiconductor.com

5

Austin Semiconductor, Inc.

following two sets of conditions (A or B) must be met to

obtain a stable supply state (stable supply defi ned as

V

CC,

V

CCQ,

V

REF,

and V

TT

are between their

minimum and maximum values as stated in Table20);

A. (single power source) The V

CC voltage ramp from

300mV to V

CC (MIN) must take no longer than

200ms; during the V

CC voltage ramp, |VCC - VCCQ|

± 0.3V. Once supply voltage ramping is complete

(when V

CCQ

crosses V

CC

(MIN)), Table 20

specifications apply.

•V

CC, VCCQ are driven from a single power converter

output

•V

TT is limited to 0.95V MAX

•V

REF

tracks V

CCQ/2;

V

REF

must be within

± 0.3V with respect to V

CCQ/2 during supply ramp

time

•V

CCQ > VREF at all times

B. (multiple power sources) V

CC > VCCQ must be

maintained during supply voltage ramping, for both

AC and DC levels, until supply voltage ramping

completes (V

CCQ crosses VCC [MIN]).

Once supply

voltage ramping is complete, Table 20 specifications

apply.

• Apply V

CC

before or at the same time as

V

CCQ; VCC voltage ramp time must be < 200ms

from when V

CC ramps from 300mV to VCC (MIN)

• Apply V

CCQ before or at the same time as VTT; the

V

CCQ voltage ramp time from when VCC (MIN) is

achieved to when V

CCQ (MIN) is achieved must be

<500ms; while V

CC is ramping, current can be

supplied from V

CC through the device to VCCQ

• VREF must track VCCQ/2, VREF must be within

± 0.3V with respect to V

CCQ/2 during supply ramp

time; V

CCQ > VREF must be met at all times

• Apply V

TT; The VTT voltage ramp time from when

V

CCQ (MIN) is achieved to when VTT (MIN) is achieved

must be no greater than 500ms

2.

For a minimum of 200

µs after stable power nd clock

(CK, CK#), apply NOP or DESELECT commands and

take CKE HIGH.

3.

Wait a minimum of 400ns, then issue a PRECHARGE

ALL command.

4.

Issue an LOAD MODE command to the EMR(2). (To

issue an EMR(2) command, provide LOW to BA0,

provide HIGH to BA1.)

5.

Issue a LOAD MODE command to the EMR(3). (To

issue an EMR(3) command, provide HIGH to BA0 and

BA1.)

6.

Issue an LOAD MODE command to the EMR to enable

DLL. To issue a DLL ENABLE command, provide LOW

to BA1 and A0, provide HIGH to BA0. Bits E7, E8, and

E9 can be set to “0” or “1”; Micron recommends setting

them to “0”.

7.

Issue a LOAD MODE command for DLL RESET. 200

cycles of clock input is required to lock the DLL. (To

issue a DLL RESET, provide HIGH to A8 and provide

LOW to BA1, and BA0.) CKE must be HIGH the entire

time.

8.

Issue PRECHARGE ALL command.

9.

Issue two or more REFRESH commands, followed

by a dummy WRITE.

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AS4DDR232M72PBG Datasheet(PDF) 5 Page - Austin Semiconductor

AS4DDR232M72PBG Datasheet(HTML) 5 Page - Austin Semiconductor

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