CS4953xx Data Sheet

32-bit Audio Decoder DSP Family

14

Copyright 2009 Cirrus Logic

DS705PP5

Figure 3. Serial Control Port - SPI Slave Mode Timing

Parameter

Symbol

Min

Typical

Max

Units

the actual maximum speed of the communication port may be limited by the firmware application. Flow control using

the SCP_BSY pin should be implemented to prevent overflow of the input data buffer. At boot the maximum speed

-25

MHz

SCP_CS falling to SCP_CLK rising

24

-

ns

SCP_CLK low time

20

-

ns

SCP_CLK high time

20

-

ns

Setup time SCP_MOSI input

5-

ns

Hold time SCP_MOSI input

5-

ns

SCP_CLK low to SCP_MISO output valid

-11

ns

SCP_CLK falling to SCP_IRQ rising

-20

ns

SCP_CS rising to SCP_IRQ falling

0ns

SCP_CLK low to SCP_CS rising

24

-

ns

SCP_CS rising to SCP_MISO output high-Z

-20

ns

SCP_CLK rising to SCP_BSY falling

ns

SCP_BSY

SCP_CS

SCP_CLK

SCP_MOSI

SCP_MISO

SCP_IRQ

0

12670

56

7

A6

A5

A0

R/W

MSB

LSB

MSB

LSB