CS2000-OTP

14

DS758F1

While acquiring lock, the digital loop bandwidth is automatically set to a large value. Once lock is

achieved, the digital loop bandwidth will settle to the minimum value selected by the ClkIn_BW[2:0] pa-

rameter.

5.4

Output to Input Frequency Ratio Configuration

5.4.1

time programmable memory. Selection between the four ratios is achieved by the M[1:0] mode select

integer binary portion while the remaining 20 LSBs represent the fractional binary portion. The maximum

multiplication factor is approximately 4096 with a resolution of 0.954 PPM in this configuration. See “Cal-

culating the User Defined Ratio” on page 26 for more information.

The status of internal dividers, such as the internal timing reference clock divider, are automatically taken

5.4.2

Selection of the User Defined Ratio for the dynamic ratio based Hybrid PLL Mode is made with the M[1:0]

pins (unless auto fractional N source selection is enabled; see section 5.4.5 on page 15).

In addition to the High-Resolution ratio format, a High-Multiplication format is also available. In the High-

the 20 MSBs represent the integer binary portion while the remaining 12 LSBs represent the fractional

binary portion. In this configuration, the maximum multiplication factor is approximately 1,048,575 with a

resolution of 244 PPM.

The 20.12 format is enabled by the LFRatioCfg global parameter. The 20.12 ratio format is only available

when the device is running in Hybrid PLL Mode. In Auto Fractional-N Source Selection Mode (see section

5.4.5.2 on page 16) when CLK_IN is not present the LFRatioCfg parameter is ignored and the ratio format

is 12.20.

It is recommended that the 12.20 High-Resolution format be utilized whenever the desired ratio is less

than 4096 since the output frequency accuracy of the PLL is directly proportional to the accuracy of the

Referenced Control

Parameter Definition

ClkIn_BW[2:0] ....................... “Clock Input Bandwidth (ClkIn_BW[2:0])” on page 25

Referenced Control

Parameter Definition

Ratio 0-3................................“Ratio 0 - 3” on page 23

M[1:0] ....................................“M1 and M0 Mode Pin Functionality” on page 19

Referenced Control

Parameter Definition

LockClk[1:0] .......................... “Lock Clock Ratio (LockClk[1:0])” section on page 23

LFRatioCfg ............................ “Low-Frequency Ratio Configuration (LFRatioCfg)” on page 24

FracNSrc ............................... “Fractional-N Source for Frequency Synthesizer (FracNSrc)” section on page 23