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F49L800UA Datasheet(PDF) 2 Page - Elite Semiconductor Memory Technology Inc. |
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F49L800UA Datasheet(HTML) 2 Page - Elite Semiconductor Memory Technology Inc. |
2 / 47 page ESMT F49L800UA/F49L800BA Elite Semiconductor Memory Technology Inc. Publication Date : Jan. 2008 Revision: 1.6 2/47 4. PIN CONFIGURATIONS 4.1 48-pin TSOP 4.2 Pin Description Symbol Pin Name Functions A0~A18 Address Input To provide memory addresses. DQ0~DQ14 Data Input/Output To output data when Read and receive data when Write. The outputs are in tri-state when OE or CE is high. DQ15/A-1 Q15 (Word mode) / LSB addr (Byte Mode) To bi-direction date I/O when BYTE is High To input address when BYTE is Low CE Chip Enable To activate the device when CE is low. OE Output Enable To gate the data output buffers. WE Write Enable To control the Write operations. RESET Reset Hardware Reset Pin/Sector Protect Unprotect BYTE Word/Byte selection input To select word mode or byte mode RY/ BY Ready/Busy To check device operation status VCC Power Supply To provide power GND Ground NC No connection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 F49L800U/BA A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE RESET NC NC RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 A16 BYTE GND DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE GND CE A0 |
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Similar Description - F49L800UA_08 |
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