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F25L32PA-100PHG Datasheet(PDF) 10 Page - Elite Semiconductor Memory Technology Inc.

Part # F25L32PA-100PHG
Description  3V Only 32 Mbit Serial Flash Memory with Dual
Download  36 Pages
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Manufacturer  ESMT [Elite Semiconductor Memory Technology Inc.]
Direct Link  http://www.esmt.com.tw/index.asp
Logo ESMT - Elite Semiconductor Memory Technology Inc.

F25L32PA-100PHG Datasheet(HTML) 10 Page - Elite Semiconductor Memory Technology Inc.

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ESMT
F25L32PA
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.0
10/36
Table 3: F25L32PA Block Protection Table
TOP
Status Register Bit
Protected Memory Area
Protection Level
BP2
BP1
BP0
Block Range
Address Range
0
0
0
0
None
None
Upper 1/64
0
0
1
Block 63
3F0000H –3FFFFFH
Upper 1/32
0
1
0
Block 62~63
3E0000H –3FFFFFH
Upper 1/16
0
1
1
Block 60~63
3C0000H –3FFFFFH
Upper 1/8
1
0
0
Block 56~63
380000H –3FFFFFH
Upper 1/4
1
0
1
Block 48~63
300000H –3FFFFFH
Upper 1/2
1
1
0
Block 32~63
200000H –3FFFFFH
All Blocks
1
1
1
Block 0~63
000000H –3FFFFFH
Block Protection (BP2, BP1, BP0)
The Block-Protection (BP2, BP1, BP0) bits define the size of the
memory area, as defined in Table 3, to be software protected
against any memory Write (Program or Erase) operations. The
Write Status Register (WRSR) instruction is used to program the
BP2, BP1, BP0 bits as long as WP is high or the Block-
Protection-Look (BPL) bit is 0. Chip Erase can only be executed if
Block-Protection bits are all 0. After power-up, BP2, BP1 and BP0
are set to1.
Block Protection Lock-Down (BPL)
WP
pin driven low (VIL), enables the Block-Protection-
Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP2, BP1, and BP0 bits. When the
WP
pin is driven high (VIH), the BPL bit has no effect and its
value is “Don’t Care”. After power-up, the BPL bit is reset to 0.


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