ESMT

F25L16PA

Elite Semiconductor Memory Technology Inc.

Publication Date: Jul. 2009

Revision: 1.4

10/33

Note:

3. One bus cycle is eight clock periods.

5. To continue programming to the next sequential address location, enter the 8-bit command, followed by the data to be

programmed.

6. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE .

7. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in

conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR

instruction to make both instructions effective.

8. The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE .

9. The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 20H as top memory type; third byte 15H as

memory capacity.

10. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each

other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both

instructions effective. Both EWSR and WREN can enable WRSR, user just need to execute one of it. A successful WRSR can

reset WREN.

11. The Manufacture ID and Device ID output will repeat continuously until CE terminates the instruction.

13. Dual output data: