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F25L08PA-50DIG Datasheet(PDF) 1 Page - Elite Semiconductor Memory Technology Inc. |
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F25L08PA-50DIG Datasheet(HTML) 1 Page - Elite Semiconductor Memory Technology Inc. |
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1 / 32 page  ESMT F25L08PA Operation Temperature Condition -40°C~85°C Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.3 1/32 Flash 3V Only 8 Mbit Serial Flash Memory with Dual FEATURES Single supply voltage 2.7~3.6V Standard, Dual SPI Speed - Read max frequency: 33MHz - Fast Read max frequency: 50MHz; 100MHz - Fast Read Dual max frequency: 50MHz / 100MHz (100MHz / 200MHz equivalent Dual SPI) Low power consumption - Active current: 35 mA - Standby current: 30 μ A Reliability - 100,000 typical program/erase cycles - 20 years Data Retention Program - Byte programming time: 7 μ s (typical) - Page programming time: 1.5 ms (typical) Erase - Chip erase time 10 sec (typical) - Block erase time 1 sec (typical) - Sector erase time 90 ms (typical) Page Programming - 256 byte per programmable page Auto Address Increment (AAI) WORD Programming - Decrease total chip programming time over Byte Program operations Lockable 4K bytes OTP security sector SPI Serial Interface - SPI Compatible: Mode 0 and Mode 3 End of program or erase detection Write Protect ( WP ) Hold Pin ( HOLD ) All Pb-free products are RoHS-Compliant ORDERING INFORMATION Product ID Speed Package COMMENTS F25L08PA –50PIG 50MHz 8 lead SOIC 150mil Pb-free F25L08PA –100PIG 100MHz 8 lead SOIC 150mil Pb-free F25L08PA –50PAIG 50MHz 8 lead SOIC 200mil Pb-free F25L08PA –100PAIG 100MHz 8 lead SOIC 200mil Pb-free F25L08PA –50DIG 50MHz 8 lead PDIP 300mil Pb-free F25L08PA –100DIG 100MHz 8 lead PDIP 300mil Pb-free GENERAL DESCRIPTION The F25L08PA is a 8Megabit, 3V only CMOS Serial Flash memory device. The device supports the standard Serial Peripheral Interface (SPI), and a Dual SPI. ESMT’s memory devices reliably store memory data even after 100,000 programming and erase cycles. The memory array can be organized into 4,096 programmable pages of 256 byte each. 1 to 256 byte can be programmed at a time with the Page Program instruction. The device also can be programmed to decrease total chip programming time with Auto Address Increment (AAI) programming. The device features sector erase architecture. The memory array is divided into 256 uniform sectors with 4K byte each; 16 uniform blocks with 64K byte each. Sectors can be erased individually without affecting the data in other sectors. Blocks can be erased individually without affecting the data in other blocks. Whole chip erase capabilities provide the flexibility to revise the data in the device. The device has Sector, Block or Chip Erase but no page erase. The sector protect/unprotect feature disables both program and erase operations in any combination of the sectors of the memory. |
Similar Part No. - F25L08PA-50DIG |
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Similar Description - F25L08PA-50DIG |
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