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F25L16PA Datasheet(PDF) 9 Page - Elite Semiconductor Memory Technology Inc. |
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F25L16PA Datasheet(HTML) 9 Page - Elite Semiconductor Memory Technology Inc. |
9 / 33 page ESMT F25L16PA Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2009 Revision: 1.4 9/33 INSTRUCTIONS Instructions are used to Read, Write (Erase and Program), and configure the F25L16PA. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Page Program, Auto Address Increment (AAI) Programming, Write Status Register, Sector Erase, Block Erase, or Chip Erase instructions, the Write Enable (WREN) instruction must be executed first. The complete list of the instructions is provided in Table 5. All instructions are synchronized off a high to low transition of CE . Inputs will be accepted on the rising edge of SCK starting with the most significant bit. CE must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for Read, Read ID, Read Status Register, Read Electronic Signature instructions). Any low to high transition on CE , before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to the standby mode. Instruction commands (Op Code), addresses, and data are all input from the most significant bit (MSB) first. Table 5: Device Operation Instructions Bus Cycle 1~3 1 2 3 4 5 6 N Operation Max. Freq SIN SOUT SIN SOUT SIN SOUT SIN SOUT SIN SOUT SIN SOUT SIN SOUT Read 33 MHz 03H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z X DOUT0 X DOUT1 X cont. Fast Read 0BH Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z X X X DOUT0 X cont. Fast Read Dual Output 12,13 3BH A23-A16 A15-A8 A7-A0 X DOUT0~1 cont. Sector Erase 4 (4K Byte) 20H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z - - - - - - Block Erase 4, (64K Byte) D8H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z - - - - - - Chip Erase 60H / C7H Hi-Z - - - - - - - - - - - - Page Program (PP) 02H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z DIN0 Hi-Z DIN1 Hi-Z Up to 256 bytes Hi-Z Auto Address Increment word programming 5 (AAI) ADH Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z DIN0 Hi-Z DIN1 Hi-Z - - Read Status Register (RDSR) 6 05H Hi-Z X DOUT - - - - - - - - - - Enable Write Status Register (EWSR) 7 50H Hi-Z - - - - - - - - - - - - Write Status Register (WRSR) 7 01H Hi-Z DIN Hi-Z - - -. - - - - - - - Write Enable (WREN) 10 06H Hi-Z - - - - - - - - - - - - Write Disable (WRDI)/ Exit secured OTP mode 04H Hi-Z - - - - - - - - - - - - Enter secured OTP mode (ENSO) B1H Hi-Z - - - - -. - - - - - - - Read Electronic Signature (RES) 8 ABH Hi-Z X 14H - - - - - - - - - - RES in secured OTP mode & not lock down ABH Hi-Z X 34H - - -. - - - - - - - RES in secured OTP mode & lock down ABH Hi-Z X 74H - - -. - - - - - - - Jedec Read ID (JEDEC-ID) 9 9FH Hi-Z X 8CH X 20H X 15H - - - - - - 00H Hi-Z X 8CH X 14H - - Read ID (RDID) 11 90H Hi-Z 00H Hi-Z 00H Hi-Z 01H Hi-Z X 14H X 8CH - - Enable SO to output RY/ Status during AAI (EBSY) 70H Hi-Z - - - - - - - - - - - - Disable SO to output RY/ Status during AAI (DBSY) 50MHz 100MHz 80H Hi-Z - - - - - - - - - - - - |
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