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F25L008A-100PAG Datasheet(PDF) 10 Page - Elite Semiconductor Memory Technology Inc. |
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F25L008A-100PAG Datasheet(HTML) 10 Page - Elite Semiconductor Memory Technology Inc. |
10 / 32 page ESMT F25L008A Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 Revision: 1.6 10/32 instructions effective. 9. The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE . 10. The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 20H as top memory type; third byte 14H as memory capacity. 11. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both instructions effective. Both EWSR and WREN can enable WRSR, user just need to execute one of it. A successful WRSR can reset WREN. Read (33 MHz) The Read instruction supports up to 33 MHz, it outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE . The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 8Mbit density, once the data from address location FFFFFH had been read, the next output will be from address location 00000H. The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A23-A0]. CE must remain active low for the duration of the Read cycle. See Figure 2 for the Read sequence. Figure 2 : READ SEQUENCE CE SCK SI 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63 64 70 N+4 DOUT N+3 DOUT N+2 DOUT N+1 DOUT N DOUT MSB MSB MSB HIGH IMPENANCE SO 03 MODE3 MODE1 ADD. ADD. ADD. |
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