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ZLR64400 Datasheet(PDF) 77 Page - Maxim Integrated Products |
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ZLR64400 Datasheet(HTML) 77 Page - Maxim Integrated Products |
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77 / 144 page  19-4624; Rev 0; 5/09 Counter/Timer Registers ZLR64400 ROM MCU Product Specification 71 Take care when using the OR or AND commands to manipulate CTR0, bit 5 and CTR1, bits 0 and 1 (DEMODULATION mode). These instructions use a Read-Modify-Write se- quence in which the current status from the CTR0 and CTR1 registers is ORed or AND- ed with the designated value and then written back into the registers. Example: When the status of bit 5 is 1, a timer reset condition occurs. Table 35. Counter/Timer 8 Control Register (CTR0) Bit 7 6 5 4 3 2 1 0 Field T8_Enable Single/ Modulo-N Time_Out T8 _Clock Capture_INT_M ask Counter_INT_M ask P34_Out Reset 00 0 0 0 0 00 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address Bank D: 00h; Linear: D00h Bit Position Value Description [7] 0 1 T8_Enable—Disable/enable the T8 counter. Disable counter. Enable counter. Configure T8 properly before enabling it. [6] 0 1 Single Pass/Modulo-N MODULO-N mode. Counter reloads the initial value when terminal count is reached SINGLE-PASS mode. Counter stops when the terminal count is reached [5] Read: 0 1 Write: 0 1 Time_Out—This bit is set when the T8 terminal count is reached. No counter time-out occurs. Counter time-out occurred. No effect. Reset Flag to 0. Software must reset this flag before using counter/timers. [4:3] 00 01 10 11 T8 _Clock—Select the T8 input clock frequency. These bits are not reset upon Stop Mode Recovery. SCLK. SCLK ÷ 2. SCLK ÷ 4. SCLK ÷ 8. [2] 0 1 Capture_INT_Mask—Disable/enable interrupt when data is captured into either LO8 or HI8 upon a positive or negative edge detection in DEMODULATION mode. This bit is not reset upon Stop Mode Recovery. Disable data capture interrupt. Enable data capture interrupt. Note: |
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