Electronic Components Datasheet Search |
|
MAX16047 Datasheet(PDF) 44 Page - Maxim Integrated Products |
|
MAX16047 Datasheet(HTML) 44 Page - Maxim Integrated Products |
44 / 61 page 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers 44 ______________________________________________________________________________________ I2C/SMBus-Compatible Serial Interface The MAX16047/MAX16049 feature an I2C/SMBus-com- patible 2-wire serial interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate bidirectional communication between the MAX16047/MAX16049 and the master device at clock rates up to 400kHz. Figure 1 shows the 2-wire interface timing diagram. The MAX16047/MAX16049 are trans- mit/receive slave-only devices, relying upon a master device to generate a clock signal. The master device (typically a µC) initiates a data transfer on the bus and generates SCL to permit that transfer. A master device communicates to the MAX16047/ MAX16049 by transmitting the proper address followed by command and/or data words. The slave address input, A0, is capable of detecting four different states, allowing multiple identical devices to share the same seri- al bus. The slave address is described further in the Slave Address section. Each transmit sequence is framed by a START (S) or REPEATED START (SR) condition and a STOP (P) condition. Each word transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse. SCL is a logic input, while SDA is an open-drain input/output. SCL and SDA both require external pullup resistors to generate the logic-high voltage. Use 4.7k Ω for most applications. Bit Transfer Each clock pulse transfers one data bit. The data on SDA must remain stable while SCL is high (Figure 9); otherwise the MAX16047/MAX16049 registers a START or STOP condition (Figure 10) from the master. SDA and SCL idle high when the bus is not busy. START and STOP Conditions Both SCL and SDA idle high when the bus is not busy. A master device signals the beginning of a transmis- sion with a START condition by transitioning SDA from high to low while SCL is high. The master device issues a STOP condition by transitioning SDA from low to high while SCL is high. A STOP condition frees the bus for another transmission. The bus remains active if a REPEATED START condition is generated, such as in the block read protocol (see Figure 1). Early STOP Conditions The MAX16047/MAX16049 recognize a STOP condition at any point during transmission except if a STOP condi- tion occurs in the same high pulse as a START condition. This condition is not a legal I2C format; at least one clock pulse must separate any START and STOP condition. REPEATED START Conditions A REPEATED START may be sent instead of a STOP condition to maintain control of the bus during a read operation. The START and REPEATED START condi- tions are functionally identical. DATA LINE STABLE, DATA VALID SDA SCL CHANGE OF DATA ALLOWED Figure 9. Bit Transfer P S START CONDITION SDA SCL STOP CONDITION Figure 10. START and STOP Conditions |
Similar Part No. - MAX16047_09 |
|
Similar Description - MAX16047_09 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |