2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs

14

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BIT 7

(MSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

(LSB)

REG

SCAN1

SCAN0

CS3

CS2

CS1

CS0

SGL/

DIF

BIT

NAME

DESCRIPTION

7

REG

Register bit. 1= setup byte (see Table 1), 0 = configuration byte.

6

SCAN1

5

SCAN0

Scan select bits. Two bits select the scanning configuration (Table 5). Defaults to 00 at power-up.

4

CS3

3

CS2

2

CS1

1

CS0

Channel select bits. Four bits select which analog input channels are to be used for conversion

(Tables 3 and 4). Defaults to 0000 at power-up. For MAX11606/MAX11607, CS3 and CS2 are

internally set to 0. For the MAX11608/MAX11609, CS3 is internally set to 0.

0SGL/

DIF

1 = single-ended, 0 = differential (Tables 3 and 4). Defaults to 1 at power-up. See the Single-

Ended/Differential Input section.

Table 2. Configuration Byte Format

CS3

1

CS2

1

CS1

CS0

AIN0

AIN1

AIN2

AIN3

2

AIN4

AIN5

AIN6

AIN7

AIN8

AIN9

AIN10 AIN11

2

GND

000

0

+

-

000

1

+

-

001

0

+

-

001

1

+

-

010

0

+

-

010

1

+

-

011

0

+

-

011

1

+

-

100

0

+

-

100

1

+-

101

0

+-

101

1

+

-

1

1

0

0

RESERVED

1

1

0

1

RESERVED

1

1

1

0

RESERVED

1

1

1

1

RESERVED

stops at AIN2 or AIN10. This does not apply to the MAX11608/MAX11609 as each provides separate pins for AIN7 and REF.

Table 3. Channel Selection in Single-Ended Mode (SGL/

DIF = 1)