DS3104GN+ datasheet(4/136 Pages) MAXIM

Part #	DS3104GN+

Description	Line Card Timing IC with Synchronous Ethernet Support

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Manufacturer	MAXIM [Maxim Integrated Products]

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4 / 136 page

________________________________________________________________________________________ DS3104-SE

19-4627; Rev 6; 5/09

4 of 136

List of Figures

Figure 2-1. Typical Application Example ..................................................................................................................... 7

Figure 3-1. Block Diagram ........................................................................................................................................... 8

Figure 7-1. DPLL Block Diagram ............................................................................................................................... 25

Figure 7-2. T0 DPLL State Transition Diagram ......................................................................................................... 27

Figure 7-3. T4 DPLL State Transition Diagram ......................................................................................................... 30

Figure 7-4. FSYNC 8kHz Options.............................................................................................................................. 44

Figure 7-5. SPI Clock Phase Options........................................................................................................................ 49

Figure 7-6. SPI Bus Transactions.............................................................................................................................. 50

Figure 9-1. JTAG Block Diagram............................................................................................................................. 117

Figure 9-2. JTAG TAP Controller State Machine .................................................................................................... 119

Figure 10-1. Recommended Termination for LVDS Pins ........................................................................................ 124

Figure 10-2. Recommended Termination for LVPECL Signals on LVDS Input Pins .............................................. 124

Figure 10-3. Recommended Termination for LVPECL-Compatible Output Pins .................................................... 125

Figure 10-4. SPI Interface Timing Diagram ............................................................................................................. 128

Figure 10-5. JTAG Timing Diagram......................................................................................................................... 129

Figure 10-6. Reset Pin Timing Diagram .................................................................................................................. 130

Figure 11-1. Pin Assignment Diagram..................................................................................................................... 132

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