________________________________________________________________________________________ DS3104-SE
19-4627; Rev 6; 5/09
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clocks of other frequencies that are phase/frequency locked to the output clock of the associated DPLL. The APLLs
multiply the clock rates from the APLL DFS blocks and simultaneously attenuate jitter. Altogether the output blocks
of the DS3104-SE can produce more than 90 different output frequencies including common SONET/SDH, PDH
and Synchronous Ethernet rates plus 2kHz and 8kHz frame-sync pulses.
The entire chip is clocked from the external oscillator connected to the REFCLK pin. Thus, the free-run and
holdover stability of the DS3104-SE is entirely a function of the stability of the external oscillator, the performance
of which can be selected to match the application: XO or TCXO. The 12.8MHz clock from the external oscillator is
multiplied by 16 by the Master Clock Generator block to create the 204.8MHz master clock used by the rest of the
device. Since every block on the device depends on the master clock and therefore the local oscillator clock for
proper operation, the master clock generator has a watchdog timer (WDT) function that can be used to signal a
local microprocessor in the event of a local oscillator clock failure.
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