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DS28EC20P+ Datasheet(PDF) 3 Page - Maxim Integrated Products |
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DS28EC20P+ Datasheet(HTML) 3 Page - Maxim Integrated Products |
3 / 27 page DS28EC20: 20Kb 1-Wire EEPROM 3 of 27 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS EEPROM Programming Current IPROG (Note 19) 0.8 mA Programming Time tPROG (Note 20) 10 ms At +25°C 200k Write/Erase Cycles (Endurance) (Notes 21, 22) NCY At +85°C (worst case) 50k ⎯ Data Retention (Notes 23, 24, 25) tDR At +85°C (worst case) 40 years Note 1: Specifications at TA = -40°C are guaranteed by design only and not production-tested. Note 2: System requirement. Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system, 1-Wire recovery times, and current requirements during EEPROM programming. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required. Note 4: Maximum value represents the internal parasite capacitance when VPUP is first applied. If a 2.2kΩ resistor is used to pull up the data line, 2.5µs after VPUP has been applied the parasite capacitance does not affect normal communications. Note 5: Guaranteed by design, characterization and/or simulation only. Not production tested. Note 6: VTL, VTH, and VHY are a function of the internal supply voltage which is itself a function of VPUP, RPUP, 1-Wire timing, and capacitive loading on I/O. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of VTL, VTH, and VHY. Note 7: Voltage below which, during a falling edge on I/O, a logic 0 is detected. Note 8: The voltage on I/O needs to be less or equal to VILMAX at all times the master is driving I/O to a logic 0 level. Note 9: Voltage above which, during a rising edge on I/O, a logic 1 is detected. Note 10: After VTH is crossed during a rising edge on I/O, the voltage on I/O has to drop by at least VHY to be detected as logic 0. Note 11: The I-V characteristic is approximately linear for voltages less than 1V. Note 12: Applies to a single device attached to a 1-Wire line. Note 13: The earliest recognition of a negative edge is possible at tREH after VTH has been reached on the preceding rising edge. Note 14: Defines maximum possible bit rate. Equal to 1/(tW0LMIN + tRECMIN). Note 15: Interval after tRSTL during which a bus master is guaranteed to sample a logic 0 on I/O if there is a DS28EC20 present. Minimum limit is tPDHMAX; maximum limit is tPDHMIN + tPDLMIN. Note 16: Highlighted numbers are NOT in compliance with legacy 1-Wire product standards. See comparison table below. Note 17: ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to VTH. The actual maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively. Note 18: δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to the input high threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF. Note 19: Current drawn from I/O during the EEPROM programming interval. During a programming cycle the voltage at I/O drops by IPROG × RPUP below VPUP. If VPUP and RPUP are within their EC table limits, the residual I/O voltage meets the guaranteed-by-design minimum voltage requirements for programming. Note 20: The tPROG interval begins tREHMAX after the trailing rising edge on I/O for the last time slot of the E/S byte for a valid copy scratchpad sequence. Interval ends once the device's self-timed EEPROM programming cycle is complete and the current drawn by the device has returned from IPROG to IL. Note 21: Write-cycle endurance is degraded as TA increases. Note 22: Not 100% production-tested; guaranteed by reliability monitor sampling. Note 23: Data retention is degraded as TA increases. Note 24: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data sheet limit at operating temperature range is established by reliability testing. Note 25: EEPROM writes may become nonfunctional after the data retention time is exceeded. Long-time storage at elevated temperatures is not recommended; the device may lose its write capability after 10 years at +125°C or 40 years at +85°C. LEGACY VALUES DS28EC20 VALUES PARAMETER STANDARD SPEED OVERDRIVE SPEED# STANDARD SPEED OVERDRIVE SPEED# MIN MAX MIN MAX MIN MAX MIN MAX tSLOT (incl. tREC) 61µs (undefined) 7µs (undefined) 65µs* (undefined) 8µs* (undefined) tRSTL 480µs (undefined) 48µs 80µs 480µs 640µs 48µs 80µs tPDH 15µs 60µs 2µs 6µs 15µs 60µs 2µs 6µs tPDL 60µs 240µs 8µs 24µs 60µs 240µs 8µs 24µs tW0L 60µs 120µs 6µs 16µs 60µs 120µs 6µs 15.5µs * Intentional change, longer recovery time requirement due to modified 1-Wire front-end. # For operation at overdrive speed, the DS28EC20 requires VPUP to be 5V ±5%. |
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