PIO Access Read [F5h]

This command reads the PIO logical status and reports

it together with the state of the PIO output latch in an

endless loop. A PIO Access Read can be terminated at

any time with a 1-Wire reset. PIO Access Read can be

executed in the Chain ON and Chain DONE state.

While the device is in the Chain ON or Chain DONE

state, the PIO output latch states always read out as 1s;

the PIO pin state may not be reported correctly.

The state of both PIO channels is sampled at the same

time. The first sampling occurs during the last (most

significant) bit of the command code F5h. The PIO sta-

tus is then reported to the bus master. While the master

receives the last (most significant) bit of the PIO status

byte, the next sampling occurs and so on until the mas-

ter generates a 1-Wire reset. The sampling occurs with

the previous byte, as shown in Figure 6. The value of

“x” is approximately 0.2µs.

PIO Access Write [A5h]

The PIO Access Write command writes to the PIO out-

put latches, which control the pulldown transistors of

the PIO channels. In an endless loop, this command

first writes new data to the PIO and then reads back the

PIO status. This implicit read-after-write can be used by

the master for status verification. A PIO Access Write

can be terminated at any time with a 1-Wire reset. The

PIO Access Write command is ignored by the device

while in Chain ON or Chain DONE state.

After the command code, the master transmits a PIO

output data byte that determines the new state of the

PIO output transistors. The first (least significant) bit is

associated to PIOA; the next bit affects PIOB. The other

6 bits of the new state byte do not have corresponding

PIO pins. These bits should always be transmitted as 1s.

To switch the output transistor on, the corresponding bit

value is 0. To switch the output transistor off (non-con-

ducting), the bit must be 1. This way the bit transmitted

1-Wire Digital Thermometer with

Sequence Detect and PIO

______________________________________________________________________________________

11

PIO Status Bit Assignment

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

COMPLEMENT OF B3 TO B0

PIOB OUTPUT

LATCH STATE

PIOB PIN

STATE

PIOA OUTPUT

LATCH STATE

PIOA PIN

STATE

PIO Output Data Bit Assignment

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

X

X

X

X

X

X

PIOB

PIOA

SAMPLING POINT**

IO

*THE "PREVIOUS BYTE" COULD BE THE COMMAND CODE OR THE DATA BYTE RESULTING FROM THE PREVIOUS PIO SAMPLE.

**THE SAMPLE POINT TIMING ALSO APPLIES TO THE PIO ACCESS WRITE COMMAND, WITH THE "PREVIOUS BYTE" BEING THE WRITE CONFIRMATION BYTE (AAh).

MOST SIGNIFICANT 2 BITS OF PREVIOUS BYTE*

LEAST SIGNIFICANT 2 BITS OF PIO STATUS BYTE

Figure 6. PIO Access Read Timing Diagram