CSF8001GMb

Rev. -

1/23/97

10/100 LAN Interface Module with

Common Mode Termination

The circuit below is a guideline for interconnecting PCA’s EPF8001GM with National DP83840A and DP83223(A) twister

chip set for 10/100 Mb/s applications.

Further details can be obtained from the chip manufacturer application notes.

Please consult PCA for applications help regarding the SSI78Q2120 or ICS1890 series parts or consult with the respective

application notes.

Typical insertion loss of the isolation transformer is 0.5dB. This parameter covers the entire spectrum of the encoded

signals in 10/100 protocols. Under terminated conditions, to transmit a 2V pk-pk signal across the cable, you must adjust

the TXREF resistor of the twister chip to get at least 2.12V pk-pk across pins 16-15.

Note that this part only has one series common mode choke and a shunt choke with `its center tap available at pin 12 for

the “common mode termination” via an external 75

Ω. This shunting effect may not meet the system EMI containment

needs; in such a case, system designers are highly encouraged to investigate

the use of

EPF8017GM, a part built

specifically with better common mode attenuation for applications with DP83840A and DP83223(A). Designers of the TSC

or the ICS parts may look into EPF8010GM for similar enhanced common mode attenuation.

System designers need not take the receiver side center tap to ground, via a capacitor. This may worsen EMI, specifically

if the secondary “common mode termination” is pulled to chassis ground as shown.

The phantom resistors shown around the connector have been known to suppress unwanted radiation that unused wires

pick up from the immediate environment. Their placement and use are to be considered carefully before a design is

finalized.

The “common mode termination” load of 75

Ω shown from the center taps of the secondary may be taken to chassis ground

via a cap of suitable value. This depends upon user’s design, EMI margin etc.

It is recommended that there be a neat separation of ground planes in the layout. It is generally accepted practice to limit

the plane off at least 0.05 inches away from the chip side pins of EPF8001GM. There need not be any ground plane beyond

this point.

For best results, PCB designer should design the outgoing traces preferably to be 50

Ω, balanced and well coupled to

achieve minimum radiation from these traces.

Typical Application Circuit for UTP (Excerpts from NSC DP83840A application notes)

DP83223

DP83840A

RJ45*

8

7

5

6

4

3

2

1

RXD

TXU

TD

RD

SD

RXI

TXO

PMRD

SD

PMID

Chassis

Ground

2000V

50

Ω

50

Ω

75

Ω

75

Ω

EPF8001GM

+

-

+

-

+

-

+

-

+

-

0.10µF {Note 1}

0.1µF

{Note 1}

1000pF

1000pF

Isolation Cap

Other pull down/up resistors not shown, for clarification please refer to National’s application notes.

12.1

Ω

12.1

Ω

7

5

6

10

12

11

1

2

16

14

15

Notes : 1. See text above for clarification.

2. *NIC Side is shown. Hub side connections will have crossover swapping pins 3-6 & 1-2.

E L E C T R O N I C S I N C .

TEL: (818) 892-0761

FAX: (818) 894-5791

http://www.pcainc.com

PCA ELECTRONICS, INC.

16799 SCHOENBORN ST.

NORTH HILLS, CA 91343

THIS PART IS PRODUCED UNDER LICENSE FROM NATIONAL SEMICONDUCTOR CORP.