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STE36N50-DA Datasheet(PDF) 1 Page - STMicroelectronics |
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STE36N50-DA Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 9 page  STE36N50-DA N - CHANNEL ENHANCEMENT MODE POWER MOS TRANSISTOR AND ULTRA-FAST DIODE IN ISOTOP PACKAGE s LOW GATE CHARGE MOSFET s TURBOSWITCH DIODE INCORPORATED s HIGH CURRENT POWER MODULE s AVALANCHE RUGGED TECHNOLOGY s VERY LARGE SOA - LARGE PEAK POWER CAPABILITY s EASY TO MOUNT s EXTREMELY LOW Rth JUNCTION TO CASE s VERY LOW DRAIN TO CASE CAPACITANCE s VERY LOW INTERNAL PARASITIC INDUCTANCE (TYPICALLY < 5 nH) s ISOLATED PACKAGE UL RECOGNIZED (FILE No E81743) INDUSTRIAL APPLICATIONS: s SMPS & UPS s MOTOR CONTROL s WELDING EQUIPMENT s ASYMMETRICAL HALF BRIDGE SMPS (WITH COMPLIMENTARY STE36N50-DK) September 1994 TYPE VDSS R DS(on) ID STE36N50-DA 500 V < 0. 14 Ω 36 A MOSFET ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Uni t VDS Drain-Source Volt age (VGS = 0) 500 V VDG R Drain-Gate Voltage (RGS =20 k Ω) 500 V VGS Gate-Source Voltage ± 20 V ID Drain Current (cont inuous) at T c =25 oC36 A ID Drain Current (cont inuous) at T c =100 oC24 A IDM( •) Drain Current (pulsed) 144 A Ptot Total Dissipation at Tc =25 oC 380 W Derating Factor 3.3 W/ oC Tstg St orage Temperat ure -55 to 150 oC Tj Max. Operat ing Junction Temperature 150 oC VISO I nsulat ion Withstand Voltage (AC-RMS) 2500 V ( •) Pulse width limited by safe operating area 3 2 1 4 INTERNAL SCHEMATIC DIAGRAM ISOTOP 1/9 |
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