SPT9691

TYPICAL INTERFACE CIRCUIT

The typical interface circuit using the comparator is shown in

figure 3. Although it needs few external components and is

easy to apply, there are several conditions that should be

noted to achieve optimal performance. The very high operat-

ing speeds of the comparator require careful layout, decou-

pling of supplies, and proper design of transmission lines.

Since the SPT9691 comparator is a very high frequency and

high gain device, certain layout rules must be followed to

avoid oscillations. The comparator should be soldered to the

board with component lead lengths kept as short as possible.

A ground plane should be used, while the input impedance to

the part is kept as low as possible, to decrease parasitic

feedback. If the output board traces are longer than approxi-

mately half an inch, microstripline techniques must be em-

ployed to prevent ringing on the output waveform. Also, the

microstriplines must be terminated at the far end with the

characteristic impedance of the line to prevent reflections. All

supply voltage pins should be decoupled with high frequency

capacitors as close to the device as possible. All ground pins

should be connected to the same ground plane to further

improve noise immunity and shielding. If using the SPT9691

as a single comparator, the outputs of the inactive compara-

tor can be grounded, left open or terminated with 50 Ohms to

-2 V. All outputs on the active comparator, whether used or

unused, should have identical terminations to minimize

ground current switching transients.

mended to prevent possible damage to the device in case

in place, there will be approximately a 6 mA current draw

less than a silicon diode drop away from the most negative

be a 1N5817 (Schottky) or equivalent.

Note: At no time should both inputs be allowed to float with

power applied to the device. At least one of the inputs should

be tied to a voltage within the common mode range (-4.0 to

+8.0 V) to prevent possible damage to the device. To prevent

possible latch-up during initial power up, the input voltages

should not exceed

±1 V. Additional protection diodes D3-D6

should be used on the inputs if there is the possibility of

exceeding the absolute maximum ratings of the inputs with

ease of implementation, all diodes (D1 - D6) can be 1N5817

(Schottky) or equivalent.

Figure 3 - SPT9691 Typical Interface Circuit

Figure 4 - SPT9691 Typical Interface Circuit With

Hysteresis

RL

50

Ω

-2 V

.1 µF

Q Output

Q Output

AVEE DVEE AVCC

GND

VREF

VIN

.1 µF

.1 µF

.1 µF

D1

D2

Inverting Input

D3

D4

D5

D6

+

-

Noninverting Input

LE

LE

= Represents line termination.

ECL

RL

50

Ω

RL

50

Ω

-2 V

.1 µF

Q Output

Q Output

AVEE DVEE AVCC

GND

VREF

VIN

.1 µF

.1 µF

.1 µF

D1

D2

Inverting Input

D3

D5

D6

D4

+

-

Noninverting Input

LE

LE

-1.3 V

-2 V

100

Ω

= Represents line termination.

RL

50

Ω

.1 µF

7

10/6/97