SPT9691

Figure 1 - Timing Diagram

TIMING INFORMATION

The timing diagram for the comparator is shown in figure 1.

If LE is high and LE low in the SPT9691, the comparator

tracks the input difference voltage. When LE is driven low

and LE high, the comparator outputs are latched into their

existing logic states.

SWITCHING TERMS (Refer to figure 1)

delay measured from the time the input signal crosses

the reference voltage (

± the input offset voltage) to the

50% point of an output LOW to HIGH transition.

delay measured from the time the input signal crosses

the reference voltage (

± the input offset voltage) to the

50% point of an output HIGH to LOW transition.

propagation delay measured from the 50% point of the

Latch Enable signal LOW to HIGH transition to 50%

point of an output LOW to HIGH transition.

propagation delay measured from the 50% point of the

Latch Enable signal LOW to HIGH transition to the 50%

point of an output HIGH to LOW transition.

MINIMUM HOLD TIME - The minimum time after the

negative transition of the Latch Enable signal that the

input signal must remain unchanged in order to be

acquired and held at the outputs.

MINIMUM LATCH ENABLE PULSE WIDTH - The

minimum time that the Latch Enable signal must be

HIGH in order to acquire an input signal change.

MINIMUM SET-UP TIME - The minimum time before

the negative transition of the Latch Enable signal that

an input signal change must be present in order to be

acquired and held at the outputs.

differential input and reference input voltages.

The set-up and hold times are a measure of the time required for an input signal to propagate through the

50%

50%

50%

tpL

Differential

Input Voltage

Output Q

Output Q

t

pLOL

Latch Enable

Latch Enable

+=300 mV,

=150 mV

V

OD

V

IN

V

OD

VRef ± VOS

The leading edge of the input signal (which consists of a

150 mV overdrive voltage) changes the comparator output

ignores the input status until the latch is strobed again. A

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10/6/97