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SPT7921 Datasheet(PDF) 7 Page - Cadeka Microcircuits LLC. |
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SPT7921 Datasheet(HTML) 7 Page - Cadeka Microcircuits LLC. |
7 / 11 page 7 3/10/97 SPT7921 TYPICAL INTERFACE CIRCUIT The SPT7921 requires few external components to achieve the stated operation and performance. Figure 2 shows the typical interface requirements when using the SPT7921 in normal circuit operation. The following section provides a description of the pin functions and outlines critical perfor- mance criteria to consider for achieving the optimal device performance. POWER SUPPLIES AND GROUNDING The SPT7921 requires -5.2 V and +5 V analog supply voltages. The +5 V supply is common to analog VCC and digital DVCC. A ferrite bead in series with each supply line is intended to reduce the transient noise injected into the analog VCC. These beads should be connected as closely as possible to the device. The connection between the beads and the SPT7921 should not be shared with any other device. Each power supply pin should be bypassed as closely as possible to the device. Use 0.1 µF for V EE and VCC, and 0.01 µF for DVCC (chip caps are preferred). AGND and DGND are the two grounds available on the SPT7921. These two internal grounds are isolated on the device. The use of ground planes is recommended to achieve optimum device performance. DGND is needed for the DVCC return path (40 mA typical) and for the return path for all digital output logic interfaces. AGND and DGND should be separated from each other and connected together only at the device through a ferrite bead. A Schottky or hot carrier diode connected between AGND and VEE is required. The use of separate power supplies between VCC and DVCC is not recommended due to poten- tial power supply sequencing latch-up conditions. Using the recommended interface circuit shown in figure 2 will provide optimum device performance for the SPT7921. VOLTAGE REFERENCE The SPT7921 requires the use of two voltage references: VFT and VFB. VFT is the force for the top of the voltage reference ladder (+2.5 V typ), VFB (-2.5 V typ) is the force for the bottom of the voltage reference ladder. Both voltages are applied across an internal reference ladder resistance of 800 ohms. The +2.5 V voltage source for reference VFT must be current limited to 20 mA maximum if a different driving circuit is used in place of the recommended reference circuit shown in figures 2 and 3. In addition, there are five reference ladder taps (VST, VRT1, VRT2, VRT3, and VSB). VST is the sense for the top of the reference ladder (+2.0 V), VRT2 is the midpoint of the ladder (0.0 V typ) and VSB is the sense for the bottom of the reference ladder (-2.0 V). VRT1 and VRT3 are quarter point ladder taps (+1.0 and -1.0 V typical, respectively). The voltages seen at VST and VSB are the true full scale input voltages of the device when VFT and VFB are driven to the recommended voltages (+2.5 V and -2.5 V typical respec- tively). VST and VSB should be used to monitor the actual full scale input voltage of the device. VRT1, VRT2 and VRT3 should not be driven to the expected ideal values as is commonly done with standard flash converters. When not being used, a decoupling capacitor of .01 µF connected to AGND from each tap is recommended to minimize high frequency noise injection. - 5.2 V COARSE A/D ANALOG PRESCALER SUCCESSIVE INTERPOLATION STAGE # 1 SUCCESSIVE INTERPOLATION STAGE # N 4 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D12 IC1 (REF-03) 6 5 2 4 + 5 V + VOUT Trim GND VIN 1 µF C1 .01 µF + - 10 k Ω 1 32 4 8 7 6 10 k Ω 30 k Ω 30 k Ω C19 1 µF + +5 V C18 .01 µF C17 .01 µF CLK VIN VFT VST VRT3 VRT2 VRT1 VSB VFB R 2R 2R 2R 2R R + C16 1 µF CLK VIN IC2 OP-07 C15 10 µF C14 10 µF + D1 C12 .01 µF + (TTL) (±2 V) +2.5 V -2.5 V FB +5 V AGND DGND -5.2 V (Analog) (Analog) 17 24 21 22 23 25 26 27 28 18 31 19 30 20 29 16 32 1 15 (OVERRANGE) (MSB) (LSB) 14 13 12 11 10 9 8 7 6 5 4 3 2 C13 .01 µF R1 100 Ω ± 2.5 V Max C2 .01 µF C3 .01 µF C4 .01 µF C5 .01 µF C6 .01 µF C7 .01 µF C8 .1 µF C9 .1 µF C10 C11 Notes to prevent latch-up due to power sequencing: 1) D1 = Schottky or hot carrier diode, P/N IN5817. 2) FB = Ferrite bead, Fair Rite P/N 2743001111 to be mounted as close to the device as possible. The ferrite bead to the ADC connection should not be shared with any other device. 3) C1-C13 = Chip cap (recommended) mounted as close to the device's pin as possible. 4) Use of a separate supply for VCC and DVCC is not recommended. 5) R1 provides current limiting to 45 mA. 6) C8, C9, C10 and C11 should be ten times larger than C12 and C13. 7) C10 = C11 = 0.1 µF cap in parallel with a 4.7 µF cap. Figure 2 - Typical Interface Circuit |
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