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SPT7920 Datasheet(PDF) 8 Page - Cadeka Microcircuits LLC. |
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SPT7920 Datasheet(HTML) 8 Page - Cadeka Microcircuits LLC. |
8 / 11 page 8 3/10/97 SPT7920 Figure 3 - Analog Equivalent Input Circuit The drive requirements for the analog inputs are minimal when compared to conventional Flash converters due to the SPT7920’s extremely low input capacitance of only 5 pF and very high input impedance of 300 k Ω. For example, for an input signal of ± 2 V p-p with an input frequency of 10 MHz, the peak output current required for the driving circuit is only 628 µA. CLOCK INPUT The SPT7920 is driven from a single-ended TTL input (CLK). For optimal noise performance, the clock input slew rate should be a minimum of 6 ns. Because of this, the use of fast logic is recommended. The clock input duty cycle should be 50% where possible, but performance will not be degraded if kept within the range of 40-60%. However, in any case the clock pulse width (tpwH) must be kept at 300 ns maximum to ensure proper operation of the internal track and hold ampli- fier (see timing diagram). The analog input signal is latched on the rising edge of the CLK. The clock input must be driven from fast TTL logic (VIH ≤4.5 V, TRISE <6 ns). In the event the clock is driven from a high current source, use a 100 Ω resistor in series to current limit to approximately 45 mA. DIGITAL OUTPUTS The format of the output data (D0-D11) is straight binary. (See table II.) The outputs are latched on the rising edge of CLK with a propagation delay of 14 ns (typ). There is a one clock cycle latency between CLK and the valid output data. (See timing diagram.) Table II - Output Data Information ANALOG INPUT OVERRANGE OUTPUT CODE D12 D11-DO >+2.0 V + 1/2 LSB 1 1111 1111 1111 +2.0 V -1 LSB O 1111 1111 111Ø 0.0 V O ØØØØ ØØØØ ØØØØ -2.0 V +1 LSB O OOOO OOOO OOOØ <-2.0 V O OOOO OOOO OOOO (Ø indicates the flickering bit between logic 0 and 1). The rise times and fall times of the digital outputs are not symmetrical. The propagation delay of the rise time is typi- cally 14 ns and the fall time is typically 6 ns. (See figure 4.) The nonsymmetrical rise and fall times create approximately 8 ns of invalid data. The analog input range will scale proportionally with respect to the reference voltage if a different input range is required. The maximum scaling factor for device operation is ± 20% of the recommended reference voltages of VFT and VFB. How- ever, because the device is laser trimmed to optimize perfor- mance with ± 2.5 V references, the accuracy of the device will degrade if operated beyond a ± 2% range. An example of a recommended reference driver circuit is shown in figure 2. IC1 is REF-03, the +2.5 V reference with a tolerance of 0.6% or +/- 0.015 V. The potentiometer R1 is 10 k Ω and supports a minimum adjustable range of up to 150 mV. IC2 is recommended to be an OP-07 or equivalent device. R2 and R3 must be matched to within 0.1% with good TC tracking to maintain a 0.3 LSB matching between VFT and VFB. If 0.1% matching is not met, then potentiometer R4 can be used to adjust the VFB voltage to the desired level. R1 and R4 should be adjusted such that VST and VSB are exactly +2.0 V and -2.0 V respectively. The following errors are defined: +FS error = top of ladder offset voltage = ∆(+FS -VST) -FS error = bottom of ladder offset voltage = ∆(-FS -VSB) Where the +FS (full scale) input voltage is defined as the output 1 LSB above the transition of 1—10 and 1—11 and the -FS input voltage is defined as the output 1 LSB below the transition of 0—00 and 0—01. ANALOG INPUT VIN is the analog input. The full scale input range will be 80% of the reference voltage or ±2 volts with VFB=-2.5 V and VFT=+2.5 V. VCC VEE VFT VIN |
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