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SPT7855SIS Datasheet(PDF) 1 Page - Cadeka Microcircuits LLC. |
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SPT7855SIS Datasheet(HTML) 1 Page - Cadeka Microcircuits LLC. |
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1 / 11 page  SPT7855 10-BIT, 25 MSPS, 135 mW A/D CONVERTER TECHNICAL DATA MAY 25, 2001 FEATURES • Monolithic 25 MSPS converter • 135 mW power dissipation • On-chip track-and-hold • Single +5 V power supply • TTL/CMOS outputs • 5 pF input capacitance • Low cost • Tri-state output buffers • High ESD protection: 3,500 V minimum • Selectable +3 V or +5 V logic I/O APPLICATIONS • All high-speed applications where low power dissipation is required • Video imaging • Medical imaging • IR imaging • Digital communications GENERAL DESCRIPTION The SPT7855 is a 10-bit monolithic, low-cost, ultralow- power analog-to-digital converter capable of minimum word rates of 25 MSPS. The on-chip track-and-hold func- tion assures very good dynamic performance without the need for external components. The input drive require- ments are minimized due to the SPT7855’s low input capacitance of only 5 pF. Power dissipation is extremely low at only 135 mW typical at 25 MSPS with a power supply of +5.0 V. The digital out- puts are +3 V or +5 V, and are user selectable. The SPT7855 is pin-compatible with an entire family of 10-bit, CMOS converters (SPT7835/40/50/55/60/61), which sim- plifies upgrades. The SPT7855 has incorporated propri- etary circuit design* and CMOS processing technologies to achieve its advanced performance. Inputs and outputs are TTL/CMOS-compatible to interface with TTL/CMOS logic systems. Output data format is straight binary. The SPT7855 is available in 28-lead SOIC and 32-lead small (7 mm square) TQFP packages over the commer- cial and industrial temperature ranges. *Patent pending 11-Bit SAR DAC ADC Section 1 T/H 11 11-Bit SAR DAC ADC Section 16 Auto- Zero CMP Auto- Zero CMP T/H 11 VREF 1:16 Mux 11 11 11 11 11-Bit 16:1 Mux/ Error Correction Timing and Control P1 P2 P15 P16 ADC Section 2 ADC Section 15 Reference Ladder Ref In Enable CLK In Data Valid AIN D10 Overrange D9 (MSB) D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) ... ... ... ... BLOCK DIAGRAM |
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