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12/14/99

SPT7853

TYPICAL INTERFACE CIRCUIT

Very few external components are required to achieve the

stated device performance. Figure 2 shows the typical inter-

face requirements when using the SPT7853 in normal cir-

cuit operation. The following sections provide descriptions

of the major functions and outline critical performance crite-

ria to consider for achieving the optimal device perfor-

mance.

Figure 2 – Typical Interface Circuit

The high sample rate is achieved by using multiple SAR

ADC sections in parallel, each of which samples the input

signal in sequence. Each SAR ADC uses 16 clock cycles to

complete a conversion. The clock cycles are allocated as

follows:

Table II – Clock Cycles

Clock

Operation

1

Reference zero sampling

2

Auto-zero comparison

3

Auto-calibrate comparison

4

Input sample

5-15

11-bit SAR conversion

16

Data transfer

The 16-phase clock, which is derived from the input clock,

synchronizes these events. The timing signals for adjacent

ADC sections are shifted by two clock cycles so that the

analog input is sampled on every other cycle of the input

clock by exactly one ADC section. After 16 clock periods,

the timing cycle repeats. The sample rate for the configura-

tion is one-half of the clock rate, e.g., for a 60 MHz clock

rate, the input sample rate is 30 MHz. The latency from ana-

log input sample to the corresponding digital output is 12

clock cycles.

• Since only eight comparators are used, a huge power

savings is realized.

• The auto-zero operation is done using a closed loop sys-

tem that uses multiple samples of the comparator’s

response to a reference zero.

• The auto-calibrate operation, which calibrates the gain of

the MSB reference and the LSB reference, is also done

with a closed loop system. Multiple samples of the gain

error are integrated to produce a calibration voltage for

each ADC section.

• Capacitive displacement currents, which can induce sam-

pling error, are minimized since only one comparator

samples the input during a clock cycle.

• The total input capacitance is very low since sections of

the converter which are not sampling the signal are iso-

lated from the input by transmission gates.

VOLTAGE REFERENCE

The SPT7853 requires the use of a single external voltage

reference for driving the high side of the reference ladder of

each ADC. It must be within the range of 3 V to 5 V. The

lower side of the ladder is typically tied to AGND (0.0 V), but

can be run up to 2.0 V with a second reference. The analog

input voltage range will track the total voltage difference

POWER SUPPLIES AND GROUNDING

The digital and the analog supply voltages on the SPT7853

are internally derived from a single analog supply. A sepa-

rate digital supply must be used for all interface circuitry

ground plane, as shown in figure 2, to prevent possible

latch-up condition.

OPERATING DESCRIPTION

The general architecture for the CMOS ADC is shown in the

block diagram. Each ADC uses a parallel SAR architecture.

Each contains eight identical successive approximation

ADC sections, all operating in parallel, a 16-phase clock

generator, an 11-bit 8:1 digital output multiplexer, correc-

tion logic, and a voltage reference generator which pro-

vides common reference levels for each ADC section.

+A5

+

4.7

AGND

REF IN

(+4V typ)

+D2.7V-5V DGND

Enable

+D2.7V–5V

10

10

10

OEN

DA0–9

DB0–9

DC0–9

DAV

CLK

1. Place the Ferrite bead as close to the ADC as possible.

2. All capacitors are 0.01 microfarad surface mount unless otherwise specified.

3. Place 0.01 microfarad surface mount as close to the respective decoupling pin as possible.

4. All input pins (references, analog inputs, clock input and /OEN) must be protected to

within the specified absolute maximum ratings.

NOTES:

Clock

Input

Ferrite Bead

AGND

DGND

Hi-Z