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T15L256A-70D Datasheet(PDF) 4 Page - Taiwan Memory Technology |
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T15L256A-70D Datasheet(HTML) 4 Page - Taiwan Memory Technology |
4 / 10 page TE CH tm T15L256A Taiwan Memory Technology, Inc. reserves the right P. 4 Publication Date: APR. 2001 to change products or specifications without notice. Revision:C AC CHARACTERISTICS (Vcc =3.3V ± 5%, Vss = 0V, Ta = 0 to 70°C) (1) READ CYCLE T15M256A-35 T15M256A-70 PARAMETER SYM. MIN. MAX. MIN. MAX. UNIT Read Cycle Time T RC 35 - 70 - ns Address Access Time T AA - 35 - 70 ns Chip Select Access Time TACS - 35 - 70 ns Output Enable to Output Valid T AOE - 25 - 35 ns Chip Selection to Output in Low Z T CLZ* 3 - 3 - ns Output Enable to Output in Low Z T OLZ ∗ 0 - 0 - ns Chip Deselection to Output in High Z T CHZ* - 25 - 35 ns Output Disable to Output in High Z T OHZ ∗ - 25 - 35 ns Output Hold from Address Change T OH 3 - 3 - ns * These parameters are sampled but not 100% tested. (2)WRITE CYCLE T15M256A-35 T15M256A-70 PARAMETER SYM. MIN. MAX. MIN. MAX. UNIT Write Cycle Time T WC 35 - 70 - ns Chip Selection to End of Write TCW 30 - 60 - ns Address Valid to End of Write T AW 30 - 60 - ns Address Setup Time T AS 0 - 0 - ns Write Pulse Width TWP 25 - 50 - ns Write Recovery Time TWR 0 - 0 - ns Data Valid to End of Write T DW 20 - 30 - ns Data Hold from End of Write T DH 0 - 0 - ns Write to Output in High Z T WHZ ∗ - 10 - 25 ns Output Disable to Output in High Z T OHZ ∗ - 10 - 25 ns Output Active from End of Write T OW 0 - 0 - ns * These parameters are sampled but not 100% tested. |
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