T15M1024A-55D datasheet(6/13 Pages) TMT

Part #	T15M1024A-55D

Description	128K X 8 LOW POWER CMOS STATIC RAM

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Manufacturer	TMT [Taiwan Memory Technology]

Direct Link	http://www.tmtech.com.tw

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6 / 13 page

TE

CH

tm

T15M1024A

TM Technology Inc. reserves the right

P. 6

Publication Date: FEB. 2002

to change products or specifications without notice.

Revision:A

AC CHARACTERISTICS

(Vcc= +5V / ±10%, Gnd = 0V, Ta = 0 ~ +70 °C /-40°C to 85°C)

(1) READ CYCLE

-55

-70

-100

PARAMETER

SYM.

Min

Max

Min

Max

Min

Max

UNIT

Read Cycle Time

tRC

55

-

70

-

100

-

ns

Address Access Time

tAA

-

55

-

70

-

100

ns

Chip Enable Access Time

tACE

-

55

-

70

-

100

ns

Output Enable Access Time

tOE

-

25

-

35

-

50

ns

Output Hold from Address Change

tOH

10

-

10

-

10

-

ns

Chip Enable to Output in Low-Z

tLZ

10

-

10

-

10

-

ns

Chip Disable to Output in High-Z

tHZ

-

20

-

25

-

30

ns

Output Enable to Output in Low-Z

tOLZ

5

-

5

-

5

-

ns

Output Disable to Output in High-Z tOHZ

-

20

-

25

-

30

ns

(2)WRITE CYCLE

-55

-70

-100

PARAMETER

SYM.

Min

Max

Min

Max

Min

Max

UNIT

Write Cycle Time

tWC

55

-

70

-

100

-

ns

Chip Enable to Write End

tCW

50

-

60

-

80

-

ns

Address Valid to Write End

tAW

50

-

60

-

80

-

ns

Address Setup Time

tAS

0

-

0

-

0

-

ns

Write Pulse Width

tWP

45

-

50

-

70

-

ns

Write Recovery Time

tWR

0

-

0

-

0

-

ns

Data Valid to Write End

tDW

25

-

30

-

40

-

ns

Data Hold Time

tDH

0

-

0

-

0

-

ns

Write Enable to Output in High-Z

tWHZ

-

25

-

25

-

30

ns

Output Active from Write End

tOW

5

-

5

-

5

-

ns

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