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T14M1024A Datasheet(PDF) 1 Page - Taiwan Memory Technology

Part No. T14M1024A
Description  128K X 8 HIGH SPEED CMOS STATIC RAM
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Manufacturer  TMT [Taiwan Memory Technology]
Direct Link  http://www.tmtech.com.tw
Logo TMT - Taiwan Memory Technology

T14M1024A Datasheet(HTML) 1 Page - Taiwan Memory Technology

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TE
CH
tm
T14M1024A
TM Technology Inc. reserves the right
P. 1
Publication Date: SEP. 2002
to change products or specifications without notice.
Revision:E
SRAM
128K X 8 HIGH SPEED
CMOS STATIC RAM
FEATURES
• Fast Address Access Times : 10/12/15ns
• Single 5V +10% power supply
• Low Power Consumption : 110/105/100mA
• TTL I/O compatible
• 2.0V data retention mode
• Automatic power-down when deselected
• Available packages :
32-pin 300 mil SOJ & 32-pin TSOP-I
• Industry Standard Pin Assignment
PIN CONFIGURATION
TSOP-I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A15
A14
A13
A12
WE
CE2
A11
VCC
NC
A10
A9
A8
A7
A6
A5
A4
OE
A16
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
A1
A2
A3
GENERAL DESCRIPTION
The T14M1024A is a one-megabit density, fast
static random access memory organized as 131,072
words by 8 bits.
It is designed for use in high
performance memory applications such as main
memory storage and high speed communication
buffers.
Fabricated using high performance CMOS
technology, access times down to 10ns are achieved.
Memory
expansion
by
banking
is
easily
accomplished using the chip enable pins CE1 and
CE2.
This device is packaged in a standard 32-pin
300 mil SOJ and 32-pin TSOP-I.
BLOCK DIAGRAM
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0 - A16
Address Inputs
I/O0 - I/O7
Data Inputs/Outputs
CE1,CE2
Chip Select Inputs
WE
Write Enable
OE
Output Enable
Vcc
Power Supply
Vss
Ground
PART NUMBER EXAMPLES
PACKAGE
SPEED
T14M1024A-10J
SOJ 300mil
10ns
T14M1024A-10P
TSOP-I 8x13.4mm 10ns
T14M1024A-10H
TSOP-I 8x20mm
10ns
A8
A9
A7
A6
A5
A3
A4
A2
A1
A0
I/O0
I/O1
A10
NC
28
27
26
25
23
24
22
21
20
19
18
17
32
29
1
2
3
4
6
5
7
8
9
10
11
12
15
16
Vcc
A12
A13
A14
A15
A16
I/O7
I/O6
I/O5
A11
CE2
WE
OE
CE1
I/O2
Vss
30
31
13
14
I/O4
I/O3
SOJ
DECODER
A0
A16
CE2
WE
OE
I/O7
Vcc
DATA I/O
CORE
ARRAY
Vss
CE1
I/O0
.
.
.
.
.
.
.


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