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T14M1024A Datasheet(PDF) 4 Page - Taiwan Memory Technology |
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T14M1024A Datasheet(HTML) 4 Page - Taiwan Memory Technology |
4 / 10 page ![]() TE CH tm T14M1024A TM Technology Inc. reserves the right P. 4 Publication Date: SEP. 2002 to change products or specifications without notice. Revision:E AC CHARACTERISTICS (Vcc=5V ± 10%, Vss = 0V, Ta = 0 to 70°C) (1) READ CYCLE T14M1024A-10 T14M1024A-12 T14M1024A-15 PARAMETER SYM. MIN. MAX. MIN. MAX. MIN. MAX. UNIT Read Cycle Time tRC 10 - 12 - 15 - ns Address Access Time tAA - 10 - 12 - 15 ns Chip Enable Access Time tACS - 10 - 12 - 15 ns Output Enable to Output Valid tAOE - 6 - 7 - 7 ns Chip Enable to Output in Low Z tCLZ* 3 - 3 - 3 - ns Output Enable to Output in Low Z tOLZ* 0 - 0 - 0 - ns Chip Disable to Output in High Z tCHZ* - 5 - 6 - 7 ns Output Disable to Output in High Z tOHZ* - 5 - 6 - 7 ns Output Hold from Address Change tOH 3 - 3 - 3 - ns * These parameters are sampled but not 100% tested. (2)WRITE CYCLE T14M1024A-10 T14M1024A-12 T14M1024A-15 PARAMETER SYM. MIN. MAX. MIN. MAX. MIN. MAX. UNIT Write Cycle Time tWC 10 - 12 - 15 - ns Chip Enable to End of Write tCW 8 - 10 - 11 - ns Address Valid to End of Write tAW 8 - 10 - 11 - ns Address Setup Time tAS 0 - 0 - 0 - ns Write Pulse Width tWP 8 - 10 - 11 - ns Write Recovery Time tWR 0 - 0 - 0 - ns Data Valid to End of Write tDW 6 - 8 - 8 - ns Data Hold from End of Write tDH 0 - 0 - 0 - ns Write to Output in High Z tWHZ* - 5 - 6 - 6 ns Output Disable to Output in High Z tOHZ* - 5 - 6 - 7 ns Output Active from End of Write tOW 0 - 0 - 0 - ns * These parameters are sampled but not 100% tested. |
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