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UCC28 Datasheet(PDF) 10 Page - Texas Instruments

Part # UCC28
Description  Low Dropout 0.5A Negative Linear Regulator
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

UCC28 Datasheet(HTML) 10 Page - Texas Instruments

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10
UCC284-5/-12/-ADJ
UCC384-5/-12/-ADJ
R3 along with C2 set the time that Q1 is allowed to be
on. Since TM is the maximum amount of time that Q1
should be allowed to stay on, an added safety margin
may be to use 0.9
• TM instead. This will ensure that Q1
is turned off in the proper amount of time. With a chosen
value for C2, R3 can be calculated as follows:
()
()
()
()
R
T
CF
n
VV
VV
M
IN
IN
3
09
21
16
=
•• −
.sec
.
l
Ohms
(8)
After the CT capacitor has charged up for a time equal to
0.9
• TM , Q1 will turn off and allow the SD/CT pin to be
pulled back to –1.5V with respect to GND through a 50k
resistor. At this point , the SD/CT pin can be used by the
UCC384 overcurrent timing control.
Minimum VIN To VOUT Delay Time
Although it may desirable to have as short a delay time
as possible, a small portion of this delay time is fixed by
the UCC384 and cannot be shortened. This is shown in
Fig. 13, where the CT capacitor has been removed from
the circuit completely, giving a fixed VIN to VOUT delay
of approximately 150
µs for a circuit with VIN = –6V and
VOUT = –5V.
Thermal Design
The Packaging Information section of this data book con-
tains reference material for the thermal ratings of various
packages. The section also includes an excellent article
entitled
Thermal Characteristics of Surface Mount Pack-
ages, which is the basis for the following discussion.
Thermal design for the UCC384 includes two modes of
operation, normal and pulsed. In normal mode, the linear
regulator and heat sink must dissipate power equal to
the maximum forward voltage drop multiplied by the
maximum load current. Assuming a constant current
load, the expected heat rise at the regulator’s junction
can be calculated as follows:
()
T
P
jc
ca
C
RISE
DISS
=•
+
°
θθ
(9)
Theta ( ) is the thermal resistance and PDISS is the
power dissipated. The junction to case thermal resis-
tance (
jc) of the SOIC-8 DP package is 22°C/W. In or-
der to prevent the regulator from going into thermal
shutdown, the case to ambient thermal resistance (
θja)
must keep the junction temperature below 150
°C. If the
UCC384 is mounted on a 5 square inch pad of 1 ounce
copper, for example, the thermal resistance (
θja)be-
comes 40-70
°C/W. If a lower thermal resistance is re-
quired by the application, the device heat sinking would
need to be improved.
When the UCC384 is in a pulsed mode, due to an
overcurrent condition, the maximum average power dis-
sipation is calculated as follows:
()
()
[]
()
()
()
P
VV
V
V
I
A
T
T
Watt
AVE
IN
OUT
PEAK
ON
ON
=
−•
sec
sec
40
s
(10)
As seen in equation 10, the average power during a fault
is reduced dramatically by the duty cycle, allowing the
heat sink to be sized for normal operation. Although the
peak power in the regulator during the TON period can be
significant, the thermal mass of the package will gener-
ally keep the junction temperature from rising unless the
TON period is increased to several milliseconds.
APPLICATION INFORMATION (cont.)
Figure 13. VIN to VOUT delay with CT capacitor
removed.
UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 FAX (603) 424-3460


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