SH7137_09 datasheet(4/24 Pages) RENESAS

Part #	SH7137

Description	Output of Complementary Pairs of PWM Signals in Three Phases

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Manufacturer	RENESAS [Renesas Technology Corp]

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SH7280 Group

MTU2: Output of Complementary Pairs of PWM Signals in Three Phases

(Complementary PWM Mode)

REJ06B0887-0100/Rev.1.00

June 2009

Page 4 of 24

A/D conversion start signals

Channels 0 to 4: TRGAN

Channel 0:

TRG0N

Channel 4:

TRG4AN

TRG4BN

Input/output pins

Channel 3: TIOC3A

TIOC3B

TIOC3C

TIOC3D

Channel 4: TIOC4A

TIOC4B

TIOC4C

TIOC4D

Input pins

Channel 5: TIC5U

TIC5V

TIC5W

Interrupt request signals

Channel 3: TGIA_3

TGIB_3

TGIC_3

TGID_3

TCIV_3

Channel 4: TGIA_4

TGIB_4

TGIC_4

TGID_4

TCIV_4

Channel 5: TGIU_5

TGIV_5

TGIW_5

Clock input

Internal clock:

MP

φ/1

MP

φ/4

MP

φ/16

MP

φ/64

MP

φ/256

MP

φ/1024

External clock: TCLKA

TCLKB

TCLKC

TCLKD

Interrupt request signals

Channel 0: TGIA_0

TGIB_0

TGIC_0

TGID_0

TGIE_0

TGIF_0

TCIV_0

Channel 1: TGIA_1

TGIB_1

TCIV_1

TCIU_1

Channel 2: TGIA_2

TGIB_2

TCIV_2

TCIU_2

Input/output pins

Channel 0: TIOC0A

TIOC0B

TIOC0C

TIOC0D

Channel 1: TIOC1A

TIOC1B

Channel 2: TIOC2A

TIOC2B

Internal data bus

[Legend]

TSTR: Timer start register

TSYR: Timer synchronous register

TCR:

Timer control register

TMDR: Timer mode register

TIOR:

Timer I/O control register

TIORH: Timer I/O control register H

TIORL: Timer I/O control register L

TIER:

Timer interrupt enable register

TGCR: Timer gate control register

TOER: Timer output master enable register

TOCR: Timer output control register

TSR:

Timer status register

TCNT: Timer counter

TCNTS:Timer subcounter

TCDR: Timer cycle data register

TCBR: Timer cycle buffer register

TDDR: Timer dead time data register

TGRA: Timer general register A

TGRB: Timer general register B

TGRC: Timer general register C

TGRD: Timer general register D

TGRE: Timer general register E

TGRF: Timer general register F

TGRU: Timer general register U

TGRV: Timer general register V

TGRW: Timer general register W

Figure 2 Block Diagram of MTU2

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