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STK17TA8
Document #: 001-52039 Rev. **
Page 7 of 23
SRAM WRITE Cycles #1 and #2
Figure 7. SRAM WRITE Cycle #1: W Controlled[7, 8]
Figure 8. SRAM WRITE Cycle #2: E Controlled[7, 8]
Notes
7. If W is low when E goes low, the outputs remain in the high-impedance state.
8. E or W must be ≥ VIH during address transitions.
NO.
Symbols
Parameter
STK17TA8-25
STK17TA8-45
Units
#1
#2
Alt.
Min
Max
Min
Max
11
tAVAV
tAVAV
tWC
Write Cycle Time
25
45
ns
13
tWLWH
tWLEH
tWP
Write Pulse Width
20
30
ns
14
tELWH
tELEH
tCW
Chip Enable to End of Write
20
30
ns
15
tDVWH
tDVEH
tDW
Data Set-up to End of Write
10
15
ns
16
tWHDX
tEHDX
tDH
Data Hold after End of Write
0
0
ns
17
tAVWH
tAVEH
tAW
Address Set-up to End of Write
20
30
ns
18
tAVWL
tAVEL
tAS
Address Set-up to Start of Write
0
0
ns
19
tWHAX
tEHAX
tWR
Address Hold after End of Write
0
0
ns
20
tWLQZ5, 7
tWZ
Write Enable to Output Disable
10
15
ns
21
tWHQX
tOW
Output Active after End of Write
3
3
ns
PREVIOUS DATA
DATA OUT
E
ADDRESS
11
tAVAV
W
16
tWHDX
DATA IN
19
tWHAX
13
tWLWH
18
tAVWL
17
tAVWH
DATA VALID
20
tWLQZ
15
tDVWH
HIGH IMPEDANCE
21
tWHQX
14
tELWH
DATA IN
11
tAVAV
16
tEHDX
13
tWLEH
19
tEHAX
18
tAVEL
17
tAVEH
DATA VALID
15
tDVEH
HIGH IMPEDANCE
14
tELEH
DATA OUT
E
ADDRESS
W
DATA IN
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