CYIL1SM4000AA
Document Number: 38-05712 Rev. *C
Page 8 of 31
Pixel Array Drivers
We have foreseen on this image sensor on-chip drivers for the
pixel array signals. Not only the driving on system level is easy
and flexible, also the maximum currents applied to the sensor are
controlled on chip. This means that the charging on sensor level
is fixed and that the sensor cannot be overdriven from externally.
The operation of the on-chip drivers is explained in detail in
Timing and Readout of Image Sensor on page 13.
Column Amplifiers
The column amplifiers are designed for minimum power
dissipation and minimum loss of signal; for this reason, multiple
biasing signals are required.
The column amplifiers also have the "voltage-averaging" feature
integrated. In case of voltage averaging mode, the voltage
average between two columns is taken and read out. In this
mode only 2:1 pixels must be read out.
To achieve the voltage-averaging mode, an additional external
digital
signal
called
"voltage-averaging"
is
required
in
combination with a bit from the SPI.
Analog to Digital Converter
The LUPA 4000 has two 10-bit Flash analog to digital converters
running nominally at 10 Msamples/s. The ADC block is
electrically separated from the image sensor. The inputs of the
ADC must be tied externally to the outputs of the output
amplifiers. If the internal ADC is not used, then the power supply
pins to the ADC and the I/Os must be grounded.
Even in this configuration, the internal ADCs are not able to
sustain the 66 Mpixel/sec provided by the output amplifier when
run at full speed.
One ADC samples the even columns and the other samples the
odd columns. Although the input range of the ADC is between
1V and 2V and the output range of the analog signal is only
between 0.3V and 1.3V, the analog output and digital input may
be tied to each other directly. This is possible because there is
an on-chip level-shifter located in front of the ADC to lift up the
analog signal to the ADC range.
ADC Timing
The ADC converts the pixel data on the falling edge of the
ADC_CLOCK but it takes 2 clock cycles before this pixel data is
at the output of the ADC. This pipeline delay is shown in Figure 8.
Figure 8. ADC Timing
Table 6. ADC Specifications
Parameter
Specification
Input range
1V - 2V [3]
Quantization
10 Bits
Nominal data rate
10 Msamples/s
DNL (linear conversion mode)
Typ < 0.4 LSB RMS
INL (linear conversion mode)
Typ < 3.5 LSB
Input capacitance
< 2 pF
Power dissipation at 33 MHz
50 mW
Conversion law
Linear/Gamma-corrected
200 ns
100 ns
Note
3. The internal ADC range is typ. 50 mV lower then the external applied ADC_VHIGH and ADC_VLOW voltages due to voltage drops over parasitic internal resistors
in the ADC.
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