LUPA-1300
Document Number: 38-05711 Rev. *C
Page 9 of 32
The photodiode is designed to obtain sensitivity as high as
possible for a dynamic range of at least 60dB. Consequently
the photodiode capacitance is 10 fF @ the output, resulting in
a S/N of more than 60 dB as the rms noise level is within the
expectation of 45 noise electrons. The pixel was specially
designed to have a very low parasitic light sensitivity (<0.5%).
The pixels are based on the high-fill factor active pixel sensor
technology of FillFactory (US patent No. 6,225,670 and
others)).
Column readout amplifiers
The column readout amplifiers are the interface between the
pixels and the output amplifiers. The pixels in the array are
selected line by line and the pixels of the selected line are
connected to the column readout amplifiers, which bring the
pixel data in the correct format to the output amplifiers.
To obtain a high frame rate, the complexity and the number of
stages in the column readout amplifiers must be minimized, so
that the power dissipation remains as low as possible, but also
to minimize the row blanking time. Figure 5 is a schematic
representation of the column readout structure. It consists of 2
parts. The first part is a module that reduces the row blanking
time. The second part shifts the signal to the correct level for
the output amplifiers and allows multiplexing in the x-direction.
From the moment that a new row is selected, the pixel data of
that row is placed onto the columns of the pixel array. These
columns are long lines and have a large parasitic capacitance.
As the pixel is small, it is not possible to match the transistor
inside the pixel, which drives this column. Consequently, the
first module in the column readout amplifiers must solve the
mismatch between the pixel driver and the large column
capacitance
Figure 5. Schematic representation of the column readout structure
Output amplifiers
16 output amplifiers each capable of working at 40 MHz pixel
rate are placed equidistant on the bottom of the image sensor.
These output amplifiers are required to obtain a frame rate of
450 frames/sec. A single output stage, not only to reduce
power, but also to achieve the required pixel rate is designed.
Figure 6 is a schematic representation of this module
Figure 6. Schematic representation of a single output stage.
Each output stage is designed to drive a load of 10 pF at a pixel
rate of 40 MHz. The load in the output stage determines this
pixel rate. In case the load capacitance is less than 10 pF, the
load in the output stage can increase, resulting in less power
dissipation of the output stages and consequently of the whole
sensor. Additionally, decreasing the load of the output stage
allows having more current available for the output stage to
Output stage
column
Module 1 : track & hold or reference set method
Module 2 : signal conditioning and multiplexing
X-mux
Shkol
Norow sel
Stabilize
power supply
Vstable
In
Out
Output stage
Cload
10 pF
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