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LTC2267CUJ-14 Datasheet(PDF) 5 Page - Linear Technology |
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LTC2267CUJ-14 Datasheet(HTML) 5 Page - Linear Technology |
5 / 32 page LTC2268-14/ LTC2267-14/LTC2266-14 5 22687614p SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode) VIH High Level Input Voltage VDD =1.8V l 1.3 V VIL Low Level Input Voltage VDD =1.8V l 0.6 V IIN Input Current VIN = 0V to 3.6V l –10 10 μA CIN Input Capacitance 3pF SDO OUTPUT (Serial Programming Mode. Open Drain Output. Requires 2kΩ Pull-Up Resistor if SDO is Used) ROL Logic Low Output Resistance to GND VDD =1.8V, SDO = 0V 200 Ω IOH Logic High Output Leakage Current SDO = 0V to 3.6V l –10 10 μA COUT Output Capacitance 3pF DIGITAL DATA OUTPUTS VOD Differential Output Voltage 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode l l 247 125 350 175 454 250 mV mV VOS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode l l 1.125 1.125 1.25 1.25 1.375 1.375 V V RTERM On-Chip Termination Resistance Termination Enabled, OVDD =1.8V 100 Ω DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS LTC2268-14 LTC2267-14 LTC2266-14 UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAX VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V IVDD Analog Supply Current Sine Wave Input l 150 TBD 119 TBD 98 TBD mA IOVDD Digital Supply Current 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode l l 16 30 TBD TBD 16 29 TBD TBD 15 29 TBD TBD mA mA PDISS Power Dissipation 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode l l 299 324 TBD TBD 243 266 TBD TBD 203 229 TBD TBD mW mW PSLEEP Sleep Mode Power 1 1 1 mW PNAP Nap Mode Power 70 70 70 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled (No Increase for Sleep Mode) 20 20 20 mW TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS LTC2268-14 LTC2267-14 LTC2266-14 UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAX fS Sampling Frequency (Notes 10, 11) l 5 125 5 105 5 80 MHz tENCL ENC Low Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 3.8 2 4 4 100 100 4.52 2 4.76 4.76 100 100 5.93 2 6.25 6.25 100 100 ns ns tENCH Analog Supply Current Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 3.8 2 4 4 100 100 4.52 2 4.76 4.76 100 100 5.93 2 6.25 6.25 100 100 ns ns tAP Sample-and-Hold Acquisition Delay Time 000 ns |
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