CYV15G0203TB
Document #: 38-02105 Rev. *C
Page 6 of 20
Pin Definitions
CYV15G0203TB Dual HOTLink II Serializer
Name
I/O Characteristics
Signal Description
Transmit Path Data and Status Signals
TXDA[9:0]
TXDB[9:0]
LVTTL Input,
synchronous,
sampled by the
associated
TXCLKx
↑ or
REFCLKx
↑[2]
Transmit Data Inputs. TXDx[9:0] data inputs are captured on the rising edge of the
transmit interface clock. The transmit interface clock is selected by the TXCKSELx
latch via the device configuration interface.
TXERRA
TXERRB
LVTTL Output,
synchronous to
REFCLKx
↑ [3],
asynchronous to
transmit channel
enable / disable,
asynchronous to loss
or return of REFCLKx±
Transmit Path Error. TXERRx is asserted HIGH to indicate detection of a transmit
Phase-Align Buffer underflow or overflow. If an underflow or overflow condition is
detected, TXERRx, for the channel in error, is asserted HIGH and remains asserted
until the transmit Phase-Align Buffer is re-centered with the PABRSTx latch via the
device configuration interface. When TXBISTx = 0, the BIST progress is presented
on the associated TXERRx output. The TXERRx signal pulses HIGH for one
transmit-character clock period to indicate a pass through the BIST sequence once
every 511 character times.
TXERRx is also asserted HIGH, when any of the following conditions is true:
• The TXPLL for the associated channel is powered down. This occurs when OE2x
and OE1x for a given channel are both disabled by setting OE2x = 0 and OE1x = 0.
• The absence of the REFCLKx± signal.
Transmit Path Clock Signals
REFCLKA±
REFCLKB±
Differential LVPECL or
single-ended
LVTTL input clock
Reference Clock. REFCLKx± clock inputs are used as the timing references for the
associated transmit PLL. These input clocks may also be selected to clock the
transmit parallel interface. When driven by a single-ended LVCMOS or LVTTL clock
source, connect the clock source to either the true or complement REFCLKx input,
and leave the alternate REFCLKx input open (floating). When driven by an LVPECL
clock source, the clock must be a differential clock, using both inputs.
TXCLKA
TXCLKB
LVTTL Clock Input,
internal pull-down
Transmit Path Input Clock. When configuration latch TXCKSELx = 0, the associated
TXCLKx input is selected as the character-rate input clock for the TXDB[9:0] input. In
this mode, the TXCLKx input must be frequency-coherent to its associated TXCLKOx
output clock, but may be offset in phase by any amount. Once initialized, TXCLKx is
allowed to drift in phase as much as ±180 degrees. If the input phase of TXCLKx drifts
beyond the handling capacity of the Phase Align Buffer, TXERRx is asserted to
indicate the loss of data, and remains asserted until the Phase Align Buffer is
initialized. The phase of the TXCLKx input clock relative to its associated REFCLKx±
is initialized when the configuration latch PABRSTx is written as 0. When the
associated TXERRx is deasserted, the Phase Align Buffer is initialized and input
characters are correctly captured.
TXCLKOA
TXCLKOB
LVTTL Output
Transmit Clock Output. TXCLKOx output clock is synthesized by each channel’s
transmit PLL and operates synchronous to the internal transmit character clock.
TXCLKOx operates at either the same frequency as REFCLKx± (TXRATEx = 0), or
at twice the frequency of REFCLKx± (TXRATEx = 1). The transmit clock outputs have
no fixed phase relationship to REFCLKx±.
Device Control Signals
RESET
LVTTL Input,
asynchronous,
internal pull-up
Asynchronous Device Reset. RESET initializes all state machines, counters, and
configuration latches in the device to a known state. RESET must be asserted LOW
for a minimum pulse width. When the reset is removed, all state machines, counters
and configuration latches are at an initial state. As per the JTAG specifications the
device RESET cannot reset the JTAG controller. Therefore, the JTAG controller has
to be reset separately. Refer to “JTAG Support” on page 10 for the methods to reset
the JTAG state machine. See Table 2 on page 10 for the initialize values of the device
configuration latches.
Notes
2. When REFCLKx± is configured for half-rate operation, these inputs are sampled relative to both the rising and falling edges of the associated REFCLKx±.
3. When REFCLKx± is configured for half-rate operation, these outputs are presented relative to both the rising and falling edges of the associated REFCLKx±.
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