CY62157EV18 MoBL®
Document #: 38-05490 Rev. *D
Page 3 of 12
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied ........................................... –55°C to + 125°C
Supply Voltage to Ground
Potential...............................–0.2V to 2.45V (VCCmax + 0.2V)
DC Voltage Applied to Outputs
in High-Z State [4, 5]..............–0.2V to 2.45V (VCCmax + 0.2V)
DC Input Voltage [4, 5] ......... –0.2V to 2.45V (VCCmax + 0.2V)
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage ......................................... > 2001V
(in accordance with MIL-STD-883, Method 3015)
Latch-up Current ................................................... > 200 mA
Operating Range
Device
Range
Ambient
Temperature
VCC [6]
CY62157EV18LL Industrial –40°C to +85°C 1.65V to 2.25V
Electrical Characteristics (Over the Operating Range)
Parameter
Description
Test Conditions
55 ns
Unit
Min
Typ [2]
Max
VOH
Output HIGH Voltage
IOH = –0.1 mA
VCC = 1.65V
1.4
V
VOL
Output LOW Voltage
IOL = 0.1 mA
VCC = 1.65V
0.2
V
VIH
Input HIGH Voltage
VCC = 1.65V to 2.25V
1.4
VCC + 0.2V
V
VIL
Input LOW Voltage
VCC = 1.65V to 2.25V
–0.2
0.4
V
IIX
Input Leakage
Current
GND < VI < VCC
–1
+1
µA
IOZ
Output Leakage
Current
GND < VO < VCC, Output Disabled
–1
+1
µA
ICC
VCC Operating Supply
Current
f = fmax = 1/tRC
VCC = VCC(max)
IOUT = 0 mA
CMOS levels
18
25
mA
f = 1 MHz
1.8
3
mA
ISB1
Automatic CEPower Down
Current–CMOS Inputs
CE1 > VCC−0.2V or CE2 < 0.2V
VIN > VCC – 0.2V, VIN < 0.2V)
f = fmax (Address and Data Only),
f = 0 (OE, WE, BHE and BLE), VCC = VCC(max).
28
µA
ISB2 [7]
Automatic CE Power Down
Current–CMOS Inputs
CE1 > VCC – 0.2V or CE2 < 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = VCC(max).
28
µA
Capacitance [8]
Parameter
Description
Test Conditions
Max
Unit
CIN
Input Capacitance
TA = 25°C, f = 1 MHz, VCC = VCC(typ)
10
pF
COUT
Output Capacitance
10
pF
Notes
4. VIL(min) = –2.0V for pulse durations less than 20 ns.
5. VIH(max) = VCC + 0.5V for pulse durations less than 20 ns.
6. Full Device AC operation assumes a 100
µs ramp time from 0 to VCC (min) and 200 µs wait time after VCC stabilization.
7. Only chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 spec. Other inputs can be left floating.
8. Tested initially and after any design or process changes that may affect these parameters.
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