PRELIMINARY
CY14E104K/CY14E104M
4 Mbit (512K x 8 / 256K x 16) nvSRAM with
Real-Time-Clock
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 001-09604 Rev. *H
Revised June 20, 2008
Features
■ 15 ns, 20 ns, 25 ns, and 45 ns access times
■ Internally organized as 512K x 8 (CY14E104K) or 256K x 16
(CY14E104M)
■ Hands off automatic STORE on power down with only a small
capacitor
■ STORE to QuantumTrap
® nonvolatile elements is initiated by
software, device pin, or AutoStore® on power down
■ RECALL to SRAM initiated by software or power up
■ High reliability
■ Infinite read, write, and recall cycles
■ 200,000 STORE cycles to QuantumTrap
■ 20 year data retention
■ Single 5V +10% operation
■ Data integrity of Cypress nvSRAM combined with full featured
Real-Time-Clock
■ Watchdog timer
■ Clock alarm with programmable interrupts
■ Capacitor or battery backup for RTC
■ Commercial and industrial temperatures
■ 44/54-pin TSOP II package
■ Pb-free and RoHS compliance
Functional Description
The Cypress CY14E104K/CY14E104M combines a 4 Mbit
nonvolatile static RAM with a full featured real-time-clock in a
monolithic
integrated
circuit.
The
embedded
nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM is read and
written an infinite number of times, while independent nonvolatile
data resides in the nonvolatile elements.
The real-time-clock function provides an accurate clock with leap
year tracking and a programmable, high accuracy oscillator. The
alarm function is programmable for one time alarms or periodic
seconds, minutes, hours, or days. There is also a programmable
watchdog timer for process control.
A0 - A18
Address
WE
OE
CE
VCC
VSS
VCAP
DQ0 - DQ7
HSB
CY14E104K
VRTCcap VRTCbat
INT
X1
X2
BHE
BLE
Logic Block Diagram
[1]
[1]
CY14E104M
Note
1. Address A0 - A18 and DQ0 - DQ7 for x8 configuration, Address A0 - A17 and Data DQ0 - DQ15 for x16 configuration.
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