PRELIMINARY
CY14E104L/CY14E104N
Document Number: 001-09603 Rev. *H
Page 9 of 22
tLZOE
[13]
tOLZ
Output Enable to Output Active
0
0
0
15
ns
tHZOE
[13]
tOHZ
Output Disable to Output Inactive
7
8
10
15
ns
tPU
[10]
tPA
Chip Enable to Power Active
0000
ns
tPD
[10]
tPS
Chip Disable to Power Standby
15
20
25
45
ns
tDBE
-
Byte Enable to Data Valid
10
10
12
20
ns
tLZBE
-
Byte Enable to Output Active
0000
ns
tHZBE
-
Byte Disable to Output Inactive
7
8
10
15
ns
SRAM Write Cycle
tWC
tWC
Write Cycle Time
15
20
25
45
ns
tPWE
tWP
Write Pulse Width
10152030
ns
tSCE
tCW
Chip Enable To End of Write
15
15
20
30
ns
tSD
tDW
Data Setup to End of Write
5
8
10
15
ns
tHD
tDH
Data Hold After End of Write
0000
ns
tAW
tAW
Address Setup to End of Write
10
15
20
30
ns
tSA
tAS
Address Setup to Start of Write
0000
ns
tHA
tWR
Address Hold After End of Write
0000
ns
tHZWE
[13,14] t
WZ
Write Enable to Output Disable
7
8
10
15
ns
tLZWE
[13]
tOW
Output Active after End of Write
3333
ns
tBW
-
Byte Enable to End of Write
15152030
ns
AutoStore/Power Up RECALL
Parameters
Description
CY14E104L/CY14E104N
Unit
Min
Max
tHRECALL
[15]
Power Up RECALL Duration
20
ms
tSTORE
[16]
STORE Cycle Duration
15
ms
VSWITCH
Low Voltage Trigger Level
4.4
V
tVCCRISE
VCC Rise Time
150
μs
AC Switching Characteristics (continued)
Parameters
Description
15 ns
20 ns
25 ns
45 ns
Unit
Cypress
Parameters
Alt
Parameters
Min
Max
Min
Max
Min
Max
Min
Max
Notes
14. If WE is low when CE goes low, the outputs remain in the high impedance state.
15. tHRECALL starts from the time VCC rises above VSWITCH.
16. If an SRAM write has not taken place since the last nonvolatile cycle, no STORE takes place.
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