CY14B108L, CY14B108N
Document #: 001-45523 Rev. *D
Page 10 of 24
AC Switching Characteristics
Parameters
Description
20 ns
25 ns
45 ns
Unit
Cypress
Parameters
Alt
Parameters
Min
Max
Min
Max
Min
Max
SRAM Read Cycle
tACE
tACS
Chip Enable Access Time
20
25
45
ns
tRC[10]
tRC
Read Cycle Time
20
25
45
ns
tAA[11]
tAA
Address Access Time
20
25
45
ns
tDOE
tOE
Output Enable to Data Valid
10
12
20
ns
tOHA[11]
tOH
Output Hold After Address Change
3
3
3
ns
tLZCE[9, 12]
tLZ
Chip Enable to Output Active
3
3
3
ns
tHZCE[9, 12]
tHZ
Chip Disable to Output Inactive
8
10
15
ns
tLZOE[9, 12]
tOLZ
Output Enable to Output Active
0
0
0
ns
tHZOE[9, 12]
tOHZ
Output Disable to Output Inactive
8
10
15
ns
tPU[9]
tPA
Chip Enable to Power Active
0
0
0
ns
tPD[9]
tPS
Chip Disable to Power Standby
20
25
45
ns
tDBE
-
Byte Enable to Data Valid
10
12
20
ns
tLZBE[9]
-
Byte Enable to Output Active
0
0
0
ns
tHZBE[9]
-
Byte Disable to Output Inactive
8
10
15
ns
SRAM Write Cycle
tWC
tWC
Write Cycle Time
20
25
45
ns
tPWE
tWP
Write Pulse Width
15
20
30
ns
tSCE
tCW
Chip Enable To End of Write
15
20
30
ns
tSD
tDW
Data Setup to End of Write
8
10
15
ns
tHD
tDH
Data Hold After End of Write
0
0
0
ns
tAW
tAW
Address Setup to End of Write
15
20
30
ns
tSA
tAS
Address Setup to Start of Write
0
0
0
ns
tHA
tWR
Address Hold After End of Write
0
0
0
ns
tHZWE[9, 12,13]
tWZ
Write Enable to Output Disable
8
10
15
ns
tLZWE[9, 12]
tOW
Output Active after End of Write
3
3
3
ns
tBW
-
Byte Enable to End of Write
15
20
30
ns
Switching Waveforms
Figure 5. SRAM Read Cycle #1: Address Controlled[10, 11, 14]
Address
Data Output
Address Valid
Previous Data Valid
Output Data Valid
t
RC
t
AA
t
OHA
Notes
10. WE must be HIGH during SRAM read cycles.
11. Device is continuously selected with CE, OE and BHE / BLE LOW.
12. Measured ±200 mV from steady state output voltage.
13. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
14. HSB must remain HIGH during READ and WRITE cycles.
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