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CY22150
Document #: 38-07104 Rev. *I
Page 9 of 16
Figure 5. Start and Stop Frame
Figure 6. Frame Format (Device Address, R/W, Register Address, Register Data
SDAT
SCLK
START
Transition
to next bit
STOP
SDAT
SCLK
DA6
DA5DA0
R/W ACK
RA7
RA6RA1
RA0
ACK
STOP
START
ACK
D7
D6
D1
D0
++
+
+
+
+
Parameter
Description
Min
Max
Unit
fSCLK
Frequency of SCLK
400
kHz
Start mode time from SDA LOW to SCL LOW
0.6
μs
CLKLOW
SCLK LOW period
1.3
μs
CLKHIGH
SCLK HIGH period
0.6
μs
tSU
Data transition to SCLK HIGH
100
ns
tDH
Data hold (SCLK LOW to data transition)
0
ns
Rise time of SCLK and SDAT
300
ns
Fall time of SCLK and SDAT
300
ns
Stop mode time from SCLK HIGH to SDAT HIGH
0.6
μs
Stop mode to Start mode
1.3
μs
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