CY22150
Document #: 38-07104 Rev. *I
Page 11 of 16
Absolute Maximum Conditions
Parameter
Description
Min
Max
Unit
VDD
Supply Voltage
–0.5
7.0
V
VDDL
I/O Supply Voltage
–0.5
7.0
V
TS
Storage Temperature[2]
–65
125
°C
TJ
Junction Temperature
125
°C
Package Power Dissipation – Commercial Temp
450
mW
Package Power Dissipation – Industrial Temp
380
mW
Digital Inputs
AVSS – 0.3
AVDD + 0.3
V
Digital Outputs Referred to VDD
VSS – 0.3
VDD + 0.3
V
Digital Outputs Referred to VDDL
VSS – 0.3
VDDL +0.3
V
ESD
Static Discharge Voltage per MIL-STD-833, Method 3015
2000
V
Recommended Operating Conditions
Parameter
Description
Min
Typ.
Max
Unit
VDD
Operating Voltage
3.135
3.3
3.465
V
VDDLHI
[3]
Operating Voltage
3.135
3.3
3.465
V
VDDLLO
[3]
Operating Voltage
2.375
2.5
2.625
V
TAC
Ambient Commercial Temp
0
70
°C
TAI
Ambient Industrial Temp
–40
85
°C
CLOAD
Max. Load Capacitance, VDD/VDDL = 3.3V
15
pF
CLOAD
Max. Load Capacitance, VDDL = 2.5V
15
pF
fREFD
Driven REF
1
133
MHz
fREFC
Crystal REF
8
30
MHz
tPU
Power up time for all VDDs to reach minimum
specified voltage (power ramps must be monotonic)
0.05
500
ms
DC Electrical Characteristics
Parameter[4]
Name
Description
Min
Typ.
Max
Unit
IOH3.3
Output High Current
VOH = VDD – 0.5, VDD/VDDL = 3.3V (sink)
12
24
mA
IOL3.3
Output Low Current
VOL = 0.5, VDD/VDDL = 3.3V (source)
12
24
mA
IOH2.5
Output High Current
VOH = VDDL – 0.5, VDDL = 2.5V (source)
8
16
mA
IOL2.5
Output Low Current
VOL = 0.5, VDDL = 2.5V (sink)
8
16
mA
VIH
Input High Voltage
CMOS levels, 70% of VDD
0.7
VDD
VIL
Input Low Voltage
CMOS levels, 30% of VDD
0.3
VDD
CIN
Input Capacitance
SCLK and SDAT Pins
7
pF
IIZ
Input Leakage Current
SCLK and SDAT Pins
5
μA
VHYS
Hysteresis of Schmitt
triggered inputs
SCLK and SDAT Pins
0.05
VDD
IVDD
[5,6]
Supply Current
AVDD/VDD Current
45
mA
IVDDL3.3
[5,6]
Supply Current
VDDL Current (VDDL = 3.465V)
25
mA
IVDDL2.5
[5,6]
Supply Current
VDDL Current (VDDL = 2.625V)
17
mA
Notes
2. Rated for 10 years.
3. VDDLis only specified and characterized at 3.3V ± 5% and 2.5V ± 5%. VDDLmay be powered at any value between 3.465V and 2.375V.
4. Not 100% tested.
5. IVDD currents specified for two CLK outputs running at 125 MHz, two LCLK outputs running at 80 MHz, and two LCLK outputs running at 66.6 MHz.
6. Use CyClocksRT to calculate actual IVDD and IVDDL for specific output frequency configurations.
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