11 / 22 page
PRELIMINARY
CY14E104L/CY14E104N
Document Number: 001-09603 Rev. *H
Page 11 of 22
Switching Waveforms
Figure 6. SRAM Read Cycle #1: Address Controlled [11, 12, 22]
Figure 7. SRAM Read Cycle #2: CE and OE Controlled [11, 22, 23]
tRC
tAA
tOHA
ADDRESS
DQ (DATA OUT)
DATA VALID
ADDRESS
tRC
CE
tACE
tLZCE
tPD
tHZCE
OE
tDOE
tLZOE
DATA VALID
ACTIVE
STANDBY
tPU
DQ (DATA OUT)
ICC
tLZBE
tDBE
tHZBE
HZOE
t
tHZCE
BHE , BLE
Notes
22. HSB must remain HIGH during read and write cycles.
23. BHE and BLE are applicable for x16 configuration only.
[+] Feedback