ADVANCE
CY14E108L, CY14E108N
Document Number: 001-45524 Rev. *A
Page 10 of 20
AutoStore and Power Up RECALL
Parameters
Description
CY14E108L/CY14E108N
Unit
Min
Max
tHRECALL
[14]
Power Up RECALL Duration
20
ms
tSTORE
[15]
STORE Cycle Duration
15
ms
VSWITCH
Low Voltage Trigger Level
4.4
V
tVCCRISE
VCC Rise Time
150
μs
Software Controlled STORE and RECALL Cycle
In the following table, the software controlled STORE/RECALL cycle parameters are listed.[16, 17]
Parameters
Description
20ns
25ns
45ns
Unit
Min
Max
Min
Max
Min
Max
tRC
STORE/RECALL Initiation Cycle Time
20
25
45
ns
tAS
Address Setup Time
0
0
0
ns
tCW
Clock Pulse Width
15
20
30
ns
tGHAX
Address Hold Time
1
1
1
ns
tRECALL
RECALL Duration
200
200
200
μs
tSS
[18, 19]
Soft Sequence Processing Time
70
70
70
μs
Hardware STORE Cycle
Parameters
Description
CY14E108L/CY14E108N
Unit
Min
Max
tDELAY
[20]
Time allowed to complete SRAM cycle
1
70
μs
tHLHX
Hardware STORE pulse width
15
ns
Switching Waveforms
Figure 5. SRAM Read Cycle #1: Address Controlled[10, 11, 21]
tRC
tAA
tOHA
ADDRESS
DQ (DATA OUT)
DATA VALID
Notes
14. tHRECALL starts from the time VCC rises above VSWITCH.
15. If an SRAM Write has not taken place since the last nonvolatile cycle, no STORE takes place.
16. The software sequence is clocked with CE controlled or OE controlled reads.
17. The six consecutive addresses must be read in the order listed in the mode selection table. WE must be HIGH during all six consecutive cycles.
18. This is the amount of time it takes to take action on a soft sequence command.Vcc power must remain HIGH to effectively register command.
19. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command
20. On a hardware STORE initiation, SRAM operation continues to be enabled for time tDELAY to allow read and write cycles to complete.
21. HSB must remain HIGH during READ and WRITE cycles.
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