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CY25200
Document #: 38-07633 Rev. *E
Page 6 of 11
Switching Waveforms
Figure 4. Duty Cycle Timing (DC = t1A/t1B)
Figure 5. Output Rise and Fall Time (SSCLK and REFCLK)
Figure 6. Power Down and Power Up Timing
Figure 7. Output Enable and Disable Timing
a
OUTPUT
Tr
VDD
0V
Tf
Output Rise time (Tr) = (0.6 x VDD)/SR1 (or SR3)
Output Fall time (Tf) = (0.6 x VDD)/SR2 (or SR4)
Refer to AC Electrical Characteristics table for SR (Slew Rate) values.
SSCLK
VDD
tPU
tSTP
VIL
VIH
POWER
DOWN
0V
(Asynchronous)
High Impedance
SSCLK
VDD
TOE1
VIL
VIH
OUTPUT
ENABLE
0V
(Asynchronous)
High Impedance
TOE2
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