PRELIMINARY
CY14E104L/CY14E104N
Document Number: 001-09603 Rev. *H
Page 4 of 22
Device Operation
The CY14E104L/CY14E104N nvSRAM is made up of two
functional components paired in the same physical cell. They are
an SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
the SRAM read and write operations are inhibited. The
CY14E104L/CY14E104N supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 200K STORE
operations.
SRAM Read
The CY14E104L/CY14E104N performs a read cycle when CE
and OE are LOW and WE and HSB are HIGH. The address
specified on pins A0-18 or A0-17 determines which of the 524,288
data bytes or 262,144 words of 16 bits each are accessed. When
the read is initiated by an address transition, the outputs are valid
after a delay of tAA (read cycle #1). If the read is initiated by CE
or OE, the outputs are valid at tACE or at tDOE, whichever is later
(read cycle #2). The data output repeatedly responds to address
changes within the tAA access time without the need for transi-
tions on any control input pins. This remains valid until another
address change or until CE or OE is brought HIGH, or WE or
HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common IO pins DQ0-15 are
written into the memory if the data is valid tSD before the end of
a WE controlled write or before the end of an CE controlled write.
It is recommended that OE be kept HIGH during the entire write
cycle to avoid data bus contention on common IO lines. If OE is
left LOW, internal circuitry turns off the output buffers tHZWE after
WE goes LOW.
AutoStore Operation
The CY14E104L/CY14E104N stores data to the nvSRAM using
one of the following three storage operations: Hardware Store
activated by HSB; Software Store activated by an address
sequence; AutoStore activated on device power down. The
AutoStore operation is a unique feature of QuantumTrap
technology
and
is
enabled
by
default
on
the
CY14E104L/CY14E104N.
During a normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, which is
below the minimum specified operating voltage, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Figure 4 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. Refer to DC Electrical
Characteristics on page 7 for the size of VCAP.
To reduce unnecessary nonvolatile stores, AutoStore and
hardware store operations are ignored unless at least one write
operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Hardware STORE (HSB) Operation
The CY14E104L/CY14E104N provides the HSB pin to control
and acknowledge the STORE operations. The HSB pin is used
to request a hardware STORE cycle. When the HSB pin is driven
LOW, the CY14E104L/CY14E104N conditionally initiates a
STORE operation after tDELAY. An actual STORE cycle begins
only if a write to the SRAM has taken place since the last STORE
or RECALL cycle. The HSB pin also acts as an open drain driver
that is internally driven LOW to indicate a busy condition when
the STORE (initiated by any means) is in progress.
SRAM read and write operations that are in progress when HSB
is driven LOW by any means are given time to complete before
the STORE operation is initiated. After HSB goes LOW, the
CY14E104L/CY14E104N
continues
SRAM
operations
for
tDELAY. During tDELAY, multiple SRAM read operations may take
place. If a write is in progress when HSB is pulled LOW it is
allowed a time, tDELAY, to complete. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH.
During any STORE operation, regardless of how it is initiated,
the CY14E104L/CY14E104N continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion
of
the
STORE
operation,
the
CY14E104L/CY14E104N remains disabled until the HSB pin
returns HIGH. Leave the HSB unconnected if it is not used.
Figure 4. AutoStore Mode
0.1uF
Vcc
V
CAP
Vcc
WE
V
CAP
V
SS
[+] Feedback
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
