Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

CY14B104KA-ZSP45XIT Datasheet(PDF) 6 Page - Cypress Semiconductor

Part # CY14B104KA-ZSP45XIT
Description  4 Mbit (512K x 8/256K x 16) nvSRAM with Real-Time-Clock
Download  31 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY14B104KA-ZSP45XIT Datasheet(HTML) 6 Page - Cypress Semiconductor

Back Button CY14B104KA-ZSP45XIT Datasheet HTML 2Page - Cypress Semiconductor CY14B104KA-ZSP45XIT Datasheet HTML 3Page - Cypress Semiconductor CY14B104KA-ZSP45XIT Datasheet HTML 4Page - Cypress Semiconductor CY14B104KA-ZSP45XIT Datasheet HTML 5Page - Cypress Semiconductor CY14B104KA-ZSP45XIT Datasheet HTML 6Page - Cypress Semiconductor CY14B104KA-ZSP45XIT Datasheet HTML 7Page - Cypress Semiconductor CY14B104KA-ZSP45XIT Datasheet HTML 8Page - Cypress Semiconductor CY14B104KA-ZSP45XIT Datasheet HTML 9Page - Cypress Semiconductor CY14B104KA-ZSP45XIT Datasheet HTML 10Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 31 page
background image
PRELIMINARY
CY14B104KA, CY14B104MA
Document #: 001-07103 Rev. *J
Page 6 of 31
Data Protection
The CY14B104KA/CY14B104MA protects data from corruption
during low voltage conditions by inhibiting all externally initiated
STORE and write operations. The low voltage condition is
detected
when
VCC is less than VSWITCH. If the
CY14B104KA/CY14B104MA is in a write mode (both CE and
WE are LOW) at power up, after a RECALL or STORE, the write
is inhibited until the SRAM is enabled after tLZHSB (HSB to output
active). This protects against inadvertent writes during power up
or brown out conditions.
Noise Considerations
Refer to CY application note AN1064.
Real-Time-Clock Operation
nvTIME Operation
The CY14B104KA/CY14B104MA offers internal registers that
contain clock, alarm, watchdog, interrupt, and control functions.
RTC registers use the last 16 address locations of the SRAM.
Internal double buffering of the clock and the clock or timer
information registers prevents accessing transitional internal
clock data during a read or write operation. Double buffering also
circumvents disrupting normal timing counts or the clock
accuracy of the internal clock when accessing clock data. Clock
and alarm registers store data in BCD format.
RTC functionality is described with respect to CY14B104KA in
the following sections. The same description applies to
CY14B104MA, except for the RTC register addresses. The RTC
register addresses for CY14B104KA range from 0x7FFF0 to
0x7FFFF, while those for CY14B104MA range from 0x3FFF0 to
0x3FFFF. Refer to Table 3 on page 10 and Table 4 on page 11
for a detailed Register Map description.
Clock Operations
The clock registers maintain time up to 9,999 years in one
second increments. The time can be set to any calendar time and
the clock automatically keeps track of days of the week and
month, leap years, and century transitions. There are eight
registers dedicated to the clock functions, which are used to set
time with a write cycle and to read time during a read cycle.
These registers contain the time of day in BCD format. Bits
defined as ‘0’ are currently not used and are reserved for future
use by Cypress.
Reading the Clock
The double buffered RTC register structure reduces the chance
of reading incorrect data from the clock. The user must stop
internal updates to the CY14B104KA time, keeping registers
before reading clock data, to prevent reading of data in transition.
Stopping the internal register updates does not affect clock
accuracy. The updating process is stopped by writing a ‘1’ to the
read bit ‘R’ (in the flags register at 0x7FFF0), and does not restart
until a ‘0’ is written to the read bit. The RTC registers are then
read while the internal clock continues to run. After a ‘0’ is written
to the read bit (‘R’), all CY14B104KA registers are simulta-
neously updated within 20 ms.
Setting the Clock
Setting the write bit ‘W’ (in the flags register at 0x7FFF0) to a ‘1’
stops updates to the time keeping registers and enables the time
to be set. The correct day, date, and time is then written into the
registers in 24 hour BCD format. The time written is referred to
as the “Base Time”. This value is stored in nonvolatile registers
and used in the calculation of the current time. Resetting the
write bit to ‘0’ transfers the register values to the actual clock
counters, after which the clock resumes normal operation.
Backup Power
The RTC in the CY14B104KA is intended for permanently
powered operation. The VRTCcap or VRTCbat pin is connected
depending on whether a capacitor or battery is chosen for the
application. When the primary power, VCC, fails and drops below
VSWITCH the device switches to the backup power supply.
The clock oscillator uses very little current, which maximizes the
backup time available from the backup source. Regardless of the
clock operation with the primary source removed, the data stored
in the nvSRAM is secure, having been stored in the nonvolatile
elements when power was lost.
During backup operation, the CY14B104KA consumes a
maximum of 300 nanoamps at 2 volts. The user must choose
capacitor or battery values according to the application. Backup
time values based on maximum current specifications are shown
in the following table. Nominal backup times are approximately
three times longer.
Using a capacitor has the advantage of recharging the backup
source each time the system is powered up. If a battery is used,
a 3V lithium is recommended and the CY14B104KA sources
current only from the battery when the primary power is removed.
The battery is not, however, recharged at any time by the
CY14B104KA. The battery capacity must be chosen for total
anticipated cumulative down time required over the life of the
system.
Stopping and Starting the Oscillator
The OSCEN bit in the calibration register at 0x7FFF8 controls
the enable and disable of the oscillator. This bit is nonvolatile and
is shipped to customers in the “enabled” (set to 0) state. To
preserve the battery life when the system is in storage, OSCEN
must be set to ‘1’. This turns off the oscillator circuit, extending
the battery life. If the OSCEN bit goes from disabled to enabled,
it takes approximately one second (two seconds maximum) for
the oscillator to start.
While system power is off, if the voltage on the backup supply
(VRTCcap or VRTCbat) falls below their respective minimum level,
the oscillator may fail.The CY14B104KA has the ability to detect
oscillator failure when system power is restored. This is recorded
in the OSCF (Oscillator Failed bit) of the flags register at the
address 0x7FFF0. When the device is powered ON (VCC goes
Table 2. RTC Backup Time
Capacitor Value
Backup Time
0.1F
72 hours
0.47F
14 days
1.0F
30 days
[+] Feedback


Similar Part No. - CY14B104KA-ZSP45XIT

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY14B104K CYPRESS-CY14B104K Datasheet
905Kb / 33P
   4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock
CY14B104K CYPRESS-CY14B104K Datasheet
1Mb / 33P
   4-Mbit (512 K 횞 8/256 K 횞 16) nvSRAM with Real Time Clock
CY14B104K CYPRESS-CY14B104K Datasheet
1Mb / 35P
   4-Mbit (512 K x 8/256 K x 16) nvSRAM with Real Time Clock 25 ns and 45 ns access times
CY14B104K-ZS20XC CYPRESS-CY14B104K-ZS20XC Datasheet
905Kb / 33P
   4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock
CY14B104K-ZS20XCT CYPRESS-CY14B104K-ZS20XCT Datasheet
905Kb / 33P
   4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock
More results

Similar Description - CY14B104KA-ZSP45XIT

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY14B104K CYPRESS-CY14B104K Datasheet
905Kb / 33P
   4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock
CY14E104K CYPRESS-CY14E104K Datasheet
732Kb / 28P
   4 Mbit (512K x 8 / 256K x 16) nvSRAM with Real-Time-Clock
CY14B108K CYPRESS-CY14B108K Datasheet
1Mb / 29P
   8 Mbit (1024K x 8/512K x 16) nvSRAM with Real Time Clock
CY14B104L CYPRESS-CY14B104L_08 Datasheet
664Kb / 22P
   4-Mbit (512K x 8/256K x 16) nvSRAM
CY14B104L CYPRESS-CY14B104L_09 Datasheet
797Kb / 25P
   4 Mbit (512K x 8/256K x 16) nvSRAM
CY14E104L CYPRESS-CY14E104L Datasheet
649Kb / 22P
   4 Mbit (512K x 8/256K x 16) nvSRAM
CY14B104L CYPRESS-CY14B104L Datasheet
415Kb / 21P
   4-Mbit (512K x 8/256K x 16) nvSRAM
CY14B104LA CYPRESS-CY14B104LA Datasheet
863Kb / 23P
   4 Mbit (512K x 8/256K x 16) nvSRAM
CY14B101KA CYPRESS-CY14B101KA_11 Datasheet
1Mb / 34P
   1 Mbit (128K x 8/64K x 16) nvSRAM with Real Time Clock
CY14B101KA CYPRESS-CY14B101KA Datasheet
972Kb / 29P
   1 Mbit (128K x 8/64K x 16) nvSRAM with Real Time Clock
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com