PRELIMINARY
CY14E104K/CY14E104M
Document #: 001-09604 Rev. *H
Page 2 of 28
Pinouts
Figure 1. Pin Diagram - TSOP II
Pin Definitions
Pin Name
IO Type
Description
A0 – A18
Input
Address Inputs Used to Select one of the 524, 288 bytes of the nvSRAM for x8 Configuration.
A0 – A17
Address Inputs Used to Select one of the 262,144 bytes of the nvSRAM for x16 Configuration.
DQ0 – DQ7 Input/Output Bidirectional Data IO Lines for x8 Configuration. Used as input or output lines depending on
operation.
DQ0 – DQ15
Bidirectional Data IO Lines for x16 Configuration. Used as input or output lines depending on
operation.
NC
No Connect
No Connects. This pin is not connected to the die.
WE
Input
Write Enable Input, Active LOW. When selected LOW, data on the IO pins is written to the address
location latched by the falling edge of CE.
CE
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. Deasserting OE HIGH causes the IO pins to tri-state.
BHE
Input
Byte High Enable, Active LOW. Controls DQ15 - DQ8.
BLE
Input
Byte Low Enable, Active LOW. Controls DQ7 - DQ0.
X1
Output
Crystal Connection. Drives crystal on start up.
X2
Input
Crystal Connection. For 32.768 kHz crystal.
VRTCcap
Power Supply Capacitor Supplied Backup RTC Supply Voltage. Left unconnected if VRTCbat is used.
VRTCbat
Power Supply Battery Supplied Backup RTC Supply Voltage. Left unconnected if VRTCcap is used.
NC
A8
X2
X1
VSS
DQ6
DQ5
DQ4
VCC
A13
DQ3
A12
DQ2
DQ1
DQ0
OE
A9
CE
NC
A0
A1
A2
A3
A4
A5
A6
A11
A7
A14
A15
A16
A17
A18
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
44 - TSOP II
Top View
(not to scale)
A10
VRTCbat
WE
DQ7
HSB
INT
VSS
VCC
VCAP
VRTCcap
(x8)
A17
DQ7
DQ6
DQ5
DQ4
VCC
DQ3
DQ2
DQ1
DQ0
NC
A0
A1
A2
A3
A4
A5
A6
A7
VCAP
WE
A8
A10
A11
A12
A13
A14
A15
A16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
54 - TSOP II
Top View
(not to scale)
OE
CE
VCC
INT
VSS
NC
A9
NC
NC
54
53
52
51
49
50
HSB
BHE
BLE
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
(x16)
VRTCcap
VRTCbat
X2
X1
[2]
[3]
[2]
[3]
Notes
2. Address expansion for 8 Mbit. NC pin not connected to die.
3. Address expansion for 16 Mbit. NC pin not connected to die.
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