CY22150
Document #: 38-07104 Rev. *I
Page 7 of 16
Although using the above table guarantees stability, it is recom-
mended to use the Print Preview function in CyClocksRT to
determine the correct charge pump settings for optimal jitter
performance.
PLL stability cannot be guaranteed for values below 16 and
above 1023. If values above 1023 are needed, use CyClocksRT
to determine the best charge pump setting.
Clock Output Settings: CLKSRC – Clock Output
Crosspoint Switch Matrix [44H(7..0)], [45H(7..0)],
[46H(7..6)]
CLKOE – Clock Output Enable Control [09H(5..0)]
Every clock output can be defined to come from one of seven
unique frequency sources. The CLKSRC(2..0) crosspoint switch
matrix defines which source is attached to each individual clock
output. CLKSRC(2..0) is set in Registers 44H, 45H, and 46H.
The remainder of register 46H(5:0) must be written with the
values stated in the register table when writing register values
46H(7:6).
In addition, each clock output has individual CLKOE control, set
by register 09H(5..0).
When DIV1N is divisible by four, then CLKSRC(0,1,0) is
guaranteed
to
be
rising
edge
phase-aligned
with
CLKSRC(0,0,1). When DIV1N is six, then CLKSRC(0,1,1) is
guaranteed
to
be
rising
edge
phase-aligned
with
CLKSRC(0,0,1).
When DIV2N is divisible by four, then CLKSRC(1,0,1) is
guaranteed
to
be
rising
edge
phase-aligned
with
CLKSRC(1,0,0). When DIV2N is divisible by eight, then
CLKSRC(1,1,0) is guaranteed to be rising edge phase-aligned
with CLKSRC(1,0,0).
Each clock output has its own output enable, controlled by
register 09H(5..0). To enable an output, set the corresponding
CLKOE bit to 1. CLKOE settings are in Table 14 on page 8.
The output swing of LCLK1 through LCLK4 is set by VDDL. The
output swing of CLK5 and CLK6 is set by VDD.
Test, Reserved, and Blank Registers
Writing to any of the following registers causes the part to exhibit
abnormal behavior, as follows.
[00H to 08H]
– Reserved
[0AH to 0BH]
– Reserved
[0DH to 11H]
– Reserved
[14H to 3FH]
– Reserved
[43H]
– Reserved
[48H to FFH]
– Reserved.
Table 11. Register 40H Change Pump Bit Settings
Address
D7
D6
D5
D4
D3
D2
D1
D0
40H
1
1
0
Pump(2)
Pump(1)
Pump(0)
PB(9)
PB(8)
Table 12. Clock Output Setting
CLKSRC2
CLKSRC1
CLKSRC0
Definition and Notes
0
0
0
Reference input.
0
0
1
DIV1CLK/DIV1N. DIV1N is defined by register [OCH]. Allowable values for DIV1N are 4
to 127. If Divider Bank 1 is not being used, set DIV1N to 8.
0
1
0
DIV1CLK/2. Fixed /2 divider option. If this option is used, DIV1N must be divisible by 4.
0
1
1
DIV1CLK/3. Fixed /3 divider option. If this option is used, set DIV1N to 6.
1
0
0
DIV2CLK/DIV2N. DIV2N is defined by Register [47H]. Allowable values for DIV2N are 4
to 127. If Divider Bank 2 is not being used, set DIV2N to 8.
1
0
1
DIV2CLK/2. Fixed /2 divider option. If this option is used, DIV2N must be divisible by 4.
1
1
0
DIV2CLK/4. Fixed /4 divider option. If this option is used, DIV2N must be divisible by 8.
1
1
1
Reserved – do not use.
Table 13. Clock Output Register Setting
Address
D7
D6
D5
D4
D3
D2
D1
D0
44H
CLKSRC2 for
LCLK1
CLKSRC1 for
LCLK1
CLKSRC0 for
LCLK1
CLKSRC2 for
LCLK2
CLKSRC1 for
LCLK2
CLKSRC0 for
LCLK2
CLKSRC2 for
LCLK3
CLKSRC1 for
LCLK3
45H
CLKSRC0 for
LCLK3
CLKSRC2 for
LCLK4
CLKSRC1 for
LCLK4
CLKSRC0 for
LCLK4
CLKSRC2 for
CLK5
CLKSRC1 for
CLK5
CLKSRC0 for
CLK5
CLKSRC2 for
CLK6
46H
CLKSRC1 for
CLK6
CLKSRC0 for
CLK6
11
11
11
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