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CY6264 Datasheet(PDF) 3 Page - Cypress Semiconductor

Part No. CY6264
Description  8K x 8 Static RAM
Download  9 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY6264 Datasheet(HTML) 3 Page - Cypress Semiconductor

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CY6264
Document #: 001-02367 Rev. *A
Page 3 of 9
AC Test Loads and Waveforms
Switching Characteristics Over the Operating Range[3]
Parameter
Description
-55
-70
Unit
Min.
Max.
Min.
Max.
READ CYCLE
tRC
Read Cycle Time
55
70
ns
tAA
Address to Data Valid
55
70
ns
tOHA
Data Hold from Address Change
5
5
ns
tACE1
CE1 LOW to Data Valid
55
70
ns
tACE2
CE2 HIGH to Data Valid
40
70
ns
tDOE
OE LOW to Data Valid
25
35
ns
tLZOE
OE LOW to Low Z
3
5
ns
tHZOE
OE HIGH to High Z[4]
20
30
ns
tLZCE1
CE1 LOW to Low Z
[5]
5
5
ns
tLZCE2
CE2 HIGH to Low Z
3
5
ns
tHZCE
CE1 HIGH to High Z
[4, 6]
CE2 LOW to High Z
20
30
ns
tPU
CE1 LOW to Power-Up
0
0
ns
tPD
CE1 HIGH to Power-Down
25
30
ns
WRITE CYCLE[6]
tWC
Write Cycle Time
50
70
ns
tSCE1
CE1 LOW to Write End
40
60
ns
tSCE2
CE2 HIGH to Write End
30
50
ns
tAW
Address Set-Up to Write End
40
55
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
25
40
ns
tSD
Data Set-Up to Write End
25
35
ns
tHD
Data Hold from Write End
0
0
ns
tHZWE
WE LOW to High Z[4]
20
30
ns
tLZWE
WE HIGH to Low Z
5
5
ns
Notes:
3. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
4. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
5. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device.
6. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. Both signals must be LOW to initiate a write and either
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
R1 481
3.0V
5V
OUTPUT
R1 481
R2
255
30 pF
GND
90%
90%
10%
< 5ns
< 5 ns
5V
OUTPUT
R2
255
5 pF
(a)
(b)
OUTPUT
1.73V
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
10%
Equivalent to:
THEVENIN EQUIVALENT
ALL INPUT PULSES
167


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